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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-06-23 18:51:51 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-09 18:54:23 +0200 |
| commit | f313211c3232a805b63687e04fdbe541ef76f5dd (patch) | |
| tree | abf1fce5caf8cf110b2d728dce5da22023ebaeea /techlibs/xilinx/cells_map.v | |
| parent | 7ed9d189079135ef53e8a19a5e3a38e240994103 (diff) | |
| download | yosys-f313211c3232a805b63687e04fdbe541ef76f5dd.tar.gz yosys-f313211c3232a805b63687e04fdbe541ef76f5dd.tar.bz2 yosys-f313211c3232a805b63687e04fdbe541ef76f5dd.zip | |
xilinx: Use dfflegalize.
Diffstat (limited to 'techlibs/xilinx/cells_map.v')
| -rw-r--r-- | techlibs/xilinx/cells_map.v | 37 |
1 files changed, 0 insertions, 37 deletions
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 97f050f76..ec4635ac6 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -18,43 +18,6 @@ * */ -// Convert negative-polarity reset to positive-polarity -(* techmap_celltype = "$_DFF_NN0_" *) -module _90_dff_nn0_to_np0 (input D, C, R, output Q); \$_DFF_NP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule -(* techmap_celltype = "$_DFF_PN0_" *) -module _90_dff_pn0_to_pp0 (input D, C, R, output Q); \$_DFF_PP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule -(* techmap_celltype = "$_DFF_NN1_" *) -module _90_dff_nn1_to_np1 (input D, C, R, output Q); \$_DFF_NP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule -(* techmap_celltype = "$_DFF_PN1_" *) -module _90_dff_pn1_to_pp1 (input D, C, R, output Q); \$_DFF_PP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule - -(* techmap_celltype = "$_DFFE_NN0P_" *) -module _90_dffe_nn0_to_np0 (input D, C, R, E, output Q); \$_DFFE_NP0P_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule -(* techmap_celltype = "$_DFFE_PN0P_" *) -module _90_dffe_pn0_to_pp0 (input D, C, R, E, output Q); \$_DFFE_PP0P_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule -(* techmap_celltype = "$_DFFE_NN1P_" *) -module _90_dffe_nn1_to_np1 (input D, C, R, E, output Q); \$_DFFE_NP1P_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule -(* techmap_celltype = "$_DFFE_PN1P_" *) -module _90_dffe_pn1_to_pp1 (input D, C, R, E, output Q); \$_DFFE_PP1P_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule - -(* techmap_celltype = "$_SDFF_NN0_" *) -module _90_dffs_nn0_to_np0 (input D, C, R, output Q); \$_SDFF_NP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule -(* techmap_celltype = "$_SDFF_PN0_" *) -module _90_dffs_pn0_to_pp0 (input D, C, R, output Q); \$_SDFF_PP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule -(* techmap_celltype = "$_SDFF_NN1_" *) -module _90_dffs_nn1_to_np1 (input D, C, R, output Q); \$_SDFF_NP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule -(* techmap_celltype = "$_SDFF_PN1_" *) -module _90_dffs_pn1_to_pp1 (input D, C, R, output Q); \$_SDFF_PP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule - -(* techmap_celltype = "$_SDFFE_NN0P_" *) -module _90_dffse_nn0_to_np0 (input D, C, R, E, output Q); \$_SDFFE_NP0P_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule -(* techmap_celltype = "$_SDFFE_PN0P_" *) -module _90_dffse_pn0_to_pp0 (input D, C, R, E, output Q); \$_SDFFE_PP0P_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule -(* techmap_celltype = "$_SDFFE_NN1P_" *) -module _90_dffse_nn1_to_np1 (input D, C, R, E, output Q); \$_SDFFE_NP1P_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule -(* techmap_celltype = "$_SDFFE_PN1P_" *) -module _90_dffse_pn1_to_pp1 (input D, C, R, E, output Q); \$_SDFFE_PP1P_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R), .E(E)); endmodule - module \$__SHREG_ (input C, input D, input E, output Q); parameter DEPTH = 0; parameter [DEPTH-1:0] INIT = 0; |