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| author | Clifford Wolf <clifford@clifford.at> | 2019-05-18 16:54:47 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-05-18 16:54:47 +0200 |
| commit | c907899422884d959632ed42c6589a0720b681e4 (patch) | |
| tree | 64bdc5903bf099d59aa9ba9dacff03d8b7a9eda2 /techlibs/xilinx/cells_map.v | |
| parent | b6345b111d994ff0de1bcd91379db1c289feb03b (diff) | |
| parent | 48ddbe52fb1428fc8f7f3d6444c5637eb151475f (diff) | |
| download | yosys-c907899422884d959632ed42c6589a0720b681e4.tar.gz yosys-c907899422884d959632ed42c6589a0720b681e4.tar.bz2 yosys-c907899422884d959632ed42c6589a0720b681e4.zip | |
Merge pull request #1017 from Kmanfi/bigger_verilog_files
Read bigger Verilog files.
Diffstat (limited to 'techlibs/xilinx/cells_map.v')
0 files changed, 0 insertions, 0 deletions