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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-11 09:25:19 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-11 09:25:19 -0700 |
| commit | bca37796578ee3a259a8327d881d5ac1264c3ac9 (patch) | |
| tree | b18c7142c3ea6f14a24367eb77d7ef10fb875464 /techlibs/xilinx/cells_map.v | |
| parent | 87b8d29a900eef6ec84c87ea7cd87f9a0b744fac (diff) | |
| download | yosys-bca37796578ee3a259a8327d881d5ac1264c3ac9.tar.gz yosys-bca37796578ee3a259a8327d881d5ac1264c3ac9.tar.bz2 yosys-bca37796578ee3a259a8327d881d5ac1264c3ac9.zip | |
Fix typo
Diffstat (limited to 'techlibs/xilinx/cells_map.v')
| -rw-r--r-- | techlibs/xilinx/cells_map.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 253678028..8bf0a28b5 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -58,7 +58,7 @@ module \$shiftx (A, B, Y); wire T0, T1; \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[a_width0-1:0]), .B(B[B_WIDTH-2:0]), .Y(T0)); \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1)); - MUXF7 fpga_mux (.I0(T0[i]), .I1(T1[i]), .S(B[B_WIDTH-1]), .O(Y[i])); + MUXF7 fpga_mux (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y)); end else if (B_WIDTH == 4) begin localparam a_width0 = 2 ** 3; |