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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-16 08:53:47 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-07-16 08:53:47 -0700 |
| commit | 5939b5d636f80d4f9345f5b8d0247332d533b68c (patch) | |
| tree | 70be983a4d1e8f0bd906faf135ecfacaabcef363 /techlibs/xilinx/cells_map.v | |
| parent | ba8ccbdea88fe432187e2481a8525cc1c53b4cf4 (diff) | |
| parent | fb062c3426e8acb5b3f54dfed7209631208fec81 (diff) | |
| download | yosys-5939b5d636f80d4f9345f5b8d0247332d533b68c.tar.gz yosys-5939b5d636f80d4f9345f5b8d0247332d533b68c.tar.bz2 yosys-5939b5d636f80d4f9345f5b8d0247332d533b68c.zip | |
Merge pull request #1188 from YosysHQ/eddie/abc9_push_inverters
abc9: push inverters driving box inputs (comb outputs) through $lut soft logic
Diffstat (limited to 'techlibs/xilinx/cells_map.v')
0 files changed, 0 insertions, 0 deletions