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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-10 09:02:42 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-10 09:02:42 -0700 |
| commit | 1ec949d5edfb6b13b8bf412763ae272a47fec894 (patch) | |
| tree | a3c82ba66e68b05769912fcf87c92883571d28c7 /techlibs/xilinx/cells_map.v | |
| parent | 526aef9c2a9d61721add1c5ef1f85d439bfbb61e (diff) | |
| download | yosys-1ec949d5edfb6b13b8bf412763ae272a47fec894.tar.gz yosys-1ec949d5edfb6b13b8bf412763ae272a47fec894.tar.bz2 yosys-1ec949d5edfb6b13b8bf412763ae272a47fec894.zip | |
Tidy up
Diffstat (limited to 'techlibs/xilinx/cells_map.v')
| -rw-r--r-- | techlibs/xilinx/cells_map.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 4f5c7ff18..ff33cf8ff 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -53,7 +53,7 @@ module \$shiftx (A, B, Y); for (i = 0; i < B_WIDTH; i++) if (i < num_mux8) \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-2), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[B_WIDTH-3:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH])); - else if (i == num_mux8 && A_WIDTH > i*a_width0) + else if (i == num_mux8 && a_widthN > 0) \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH])); else assign T[(i+1)*Y_WIDTH-1:i*Y_WIDTH] = {Y_WIDTH{1'bx}}; |