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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-15 14:18:44 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-15 14:18:44 -0700 |
| commit | 0c7ee6d0fa14b634ffbde5ad79983cb89372a697 (patch) | |
| tree | d4cb84e0aeeea75b5a939baf53d3680ade175430 /techlibs/xilinx/cells_map.v | |
| parent | 91fcf034bceecd50f1aaf96c3cdc270250ab9597 (diff) | |
| download | yosys-0c7ee6d0fa14b634ffbde5ad79983cb89372a697.tar.gz yosys-0c7ee6d0fa14b634ffbde5ad79983cb89372a697.tar.bz2 yosys-0c7ee6d0fa14b634ffbde5ad79983cb89372a697.zip | |
Move DSP mapping back out to dsp_map.v
Diffstat (limited to 'techlibs/xilinx/cells_map.v')
| -rw-r--r-- | techlibs/xilinx/cells_map.v | 41 |
1 files changed, 0 insertions, 41 deletions
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 6ebca0d54..2eb9fa2c1 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -365,44 +365,3 @@ module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1); MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O)); endmodule `endif - -module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] OUT); - wire [47:0] P_48; - DSP48E1 #( - // Disable all registers - .ACASCREG(0), - .ADREG(0), - .A_INPUT("DIRECT"), - .ALUMODEREG(0), - .AREG(0), - .BCASCREG(0), - .B_INPUT("DIRECT"), - .BREG(0), - .CARRYINREG(0), - .CARRYINSELREG(0), - .CREG(0), - .DREG(0), - .INMODEREG(0), - .MREG(0), - .OPMODEREG(0), - .PREG(0) - ) _TECHMAP_REPLACE_ ( - //Data path - .A({5'b0, A}), - .B(B), - .C(48'b0), - .D(24'b0), - .P(P_48), - - .INMODE(4'b0000), - .ALUMODE(4'b0000), - .OPMODE(7'b000101), - .CARRYINSEL(3'b000), - - .ACIN(30'b0), - .BCIN(18'b0), - .PCIN(48'b0), - .CARRYIN(1'b0) - ); - assign OUT = P_48; -endmodule |