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| author | Ruben Undheim <ruben.undheim@gmail.com> | 2016-06-18 14:13:36 +0200 |
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| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2016-06-18 14:23:38 +0200 |
| commit | a8200a773fb8cf2ce2d8793716b62e01c97dd731 (patch) | |
| tree | 45fde92e3cdd9d6bd1585fbdcc6e04076fbb4b9a /techlibs/xilinx/brams_init.py | |
| parent | 178ff3e7f6f9766f0b1a3e8dcc96e030aea59b15 (diff) | |
| download | yosys-a8200a773fb8cf2ce2d8793716b62e01c97dd731.tar.gz yosys-a8200a773fb8cf2ce2d8793716b62e01c97dd731.tar.bz2 yosys-a8200a773fb8cf2ce2d8793716b62e01c97dd731.zip | |
A few modifications after pull request comments
- Renamed Design::packages to Design::verilog_packages
- No need to include ast.h in rtlil.h
Diffstat (limited to 'techlibs/xilinx/brams_init.py')
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