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| author | Clifford Wolf <clifford@clifford.at> | 2013-03-01 01:10:11 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-03-01 01:10:11 +0100 |
| commit | 51c2b797b34e1681bc5dbfcbebc1f45ca2294c0b (patch) | |
| tree | a18a13d158a528f8cd1c115fffce905c308309e2 /techlibs/stdcells_sim.v | |
| parent | 4826dc6a8769c190ae74d2e2d22955484183d3bb (diff) | |
| download | yosys-51c2b797b34e1681bc5dbfcbebc1f45ca2294c0b.tar.gz yosys-51c2b797b34e1681bc5dbfcbebc1f45ca2294c0b.tar.bz2 yosys-51c2b797b34e1681bc5dbfcbebc1f45ca2294c0b.zip | |
Do not unescape identifiers starting with \$
Diffstat (limited to 'techlibs/stdcells_sim.v')
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