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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-12 12:57:01 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-02 07:14:08 -0700 |
| commit | fdafb74eb77e33e9fa2b4e591804d1d02c122ff9 (patch) | |
| tree | 49cd4fc4493b1ecfcf50aabda00aee1130124fa3 /techlibs/sf2 | |
| parent | 164dd0f6b298e416bd1ef882f21a4d0b5acfd039 (diff) | |
| download | yosys-fdafb74eb77e33e9fa2b4e591804d1d02c122ff9.tar.gz yosys-fdafb74eb77e33e9fa2b4e591804d1d02c122ff9.tar.bz2 yosys-fdafb74eb77e33e9fa2b4e591804d1d02c122ff9.zip | |
kernel: use more ID::*
Diffstat (limited to 'techlibs/sf2')
| -rw-r--r-- | techlibs/sf2/sf2_iobs.cc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/techlibs/sf2/sf2_iobs.cc b/techlibs/sf2/sf2_iobs.cc index 3d43332e2..57e3b0de3 100644 --- a/techlibs/sf2/sf2_iobs.cc +++ b/techlibs/sf2/sf2_iobs.cc @@ -69,10 +69,10 @@ static void handle_iobufs(Module *module, bool clkbuf_mode) buf_port = "\\D"; } else if (clkbuf_mode && clk_bits.count(canonical_bit)) { buf_type = "\\CLKBUF"; - buf_port = "\\Y"; + buf_port = ID::Y; } else { buf_type = "\\INBUF"; - buf_port = "\\Y"; + buf_port = ID::Y; } Cell *c = module->addCell(NEW_ID, buf_type); @@ -114,7 +114,7 @@ static void handle_clkint(Module *module) } if (cell->type.in("\\CLKBUF", "\\CLKBIBUF", "\\CLKBUF_DIFF", "\\GCLKBUF", "\\GCLKBUF_DIFF", "\\GCLKBIBUF", "\\CLKINT", "\\CLKINT_PRESERVE", "\\GCLKINT", "\\RCLKINT", "\\RGCLKINT")) { - for (auto bit : sigmap(cell->getPort("\\Y"))) + for (auto bit : sigmap(cell->getPort(ID::Y))) handled_clk_bits.push_back(bit); } } @@ -136,8 +136,8 @@ static void handle_clkint(Module *module) if (clk_bits.count(canonical_bit)) { Cell *c = module->addCell(NEW_ID, "\\CLKINT"); SigBit new_bit = module->addWire(NEW_ID); - c->setPort("\\A", new_bit); - c->setPort("\\Y", bit); + c->setPort(ID::A, new_bit); + c->setPort(ID::Y, bit); log("Added %s cell %s for clock signal %s.\n", log_id(c->type), log_id(c), log_signal(bit)); clk_bits.erase(canonical_bit); did_something = true; |