kernel: big fat patch to use more ID::*, otherwise ID(*)

1 files changed, 16 insertions, 16 deletions

diff --git a/techlibs/sf2/sf2_iobs.cc b/techlibs/sf2/sf2_iobs.cc
index 57e3b0de3..619888d38 100644
--- a/techlibs/sf2/sf2_iobs.cc
+++ b/techlibs/sf2/sf2_iobs.cc
@@ -34,14 +34,14 @@ static void handle_iobufs(Module *module, bool clkbuf_mode)
 
 	for (auto cell : module->cells())
 	{
-		if (clkbuf_mode && cell->type == "\\SLE") {
-			for (auto bit : sigmap(cell->getPort("\\CLK")))
+		if (clkbuf_mode && cell->type == ID(SLE)) {
+			for (auto bit : sigmap(cell->getPort(ID::CLK)))
 				clk_bits.insert(bit);
 		}
-		if (cell->type.in("\\INBUF", "\\OUTBUF", "\\TRIBUFF", "\\BIBUF", "\\CLKBUF", "\\CLKBIBUF",
-				"\\INBUF_DIFF", "\\OUTBUF_DIFF", "\\BIBUFF_DIFF", "\\TRIBUFF_DIFF", "\\CLKBUF_DIFF",
-				"\\GCLKBUF", "\\GCLKBUF_DIFF", "\\GCLKBIBUF")) {
-			for (auto bit : sigmap(cell->getPort("\\PAD")))
+		if (cell->type.in(ID(INBUF), ID(OUTBUF), ID(TRIBUFF), ID(BIBUF), ID(CLKBUF), ID(CLKBIBUF),
+				ID(INBUF_DIFF), ID(OUTBUF_DIFF), ID(BIBUFF_DIFF), ID(TRIBUFF_DIFF), ID(CLKBUF_DIFF),
+				ID(GCLKBUF), ID(GCLKBUF_DIFF), ID(GCLKBIBUF))) {
+			for (auto bit : sigmap(cell->getPort(ID(PAD))))
 				handled_io_bits.insert(bit);
 		}
 	}
@@ -65,13 +65,13 @@ static void handle_iobufs(Module *module, bool clkbuf_mode)
 			IdString buf_type, buf_port;
 
 			if (wire->port_output) {
-				buf_type = "\\OUTBUF";
-				buf_port = "\\D";
+				buf_type = ID(OUTBUF);
+				buf_port = ID::D;
 			} else if (clkbuf_mode && clk_bits.count(canonical_bit)) {
-				buf_type = "\\CLKBUF";
+				buf_type = ID(CLKBUF);
 				buf_port = ID::Y;
 			} else {
-				buf_type = "\\INBUF";
+				buf_type = ID(INBUF);
 				buf_port = ID::Y;
 			}
 
@@ -96,7 +96,7 @@ static void handle_iobufs(Module *module, bool clkbuf_mode)
 	module->rewrite_sigspecs(rewrite_function);
 
 	for (auto &it : pad_bits)
-		it.first->setPort("\\PAD", it.second);
+		it.first->setPort(ID(PAD), it.second);
 }
 
 static void handle_clkint(Module *module)
@@ -108,12 +108,12 @@ static void handle_clkint(Module *module)
 
 	for (auto cell : module->cells())
 	{
-		if (cell->type == "\\SLE") {
-			for (auto bit : sigmap(cell->getPort("\\CLK")))
+		if (cell->type == ID(SLE)) {
+			for (auto bit : sigmap(cell->getPort(ID::CLK)))
 				clk_bits.insert(bit);
 		}
-		if (cell->type.in("\\CLKBUF", "\\CLKBIBUF", "\\CLKBUF_DIFF", "\\GCLKBUF", "\\GCLKBUF_DIFF", "\\GCLKBIBUF",
-				"\\CLKINT", "\\CLKINT_PRESERVE", "\\GCLKINT", "\\RCLKINT", "\\RGCLKINT")) {
+		if (cell->type.in(ID(CLKBUF), ID(CLKBIBUF), ID(CLKBUF_DIFF), ID(GCLKBUF), ID(GCLKBUF_DIFF), ID(GCLKBIBUF),
+				ID(CLKINT), ID(CLKINT_PRESERVE), ID(GCLKINT), ID(RCLKINT), ID(RGCLKINT))) {
 			for (auto bit : sigmap(cell->getPort(ID::Y)))
 				handled_clk_bits.push_back(bit);
 		}
@@ -134,7 +134,7 @@ static void handle_clkint(Module *module)
 		for (auto &bit : sig) {
 			SigBit canonical_bit = sigmap(bit);
 			if (clk_bits.count(canonical_bit)) {
-				Cell *c = module->addCell(NEW_ID, "\\CLKINT");
+				Cell *c = module->addCell(NEW_ID, ID(CLKINT));
 				SigBit new_bit = module->addWire(NEW_ID);
 				c->setPort(ID::A, new_bit);
 				c->setPort(ID::Y, bit);