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| author | Lofty <dan.ravensloft@gmail.com> | 2021-04-12 10:33:40 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-04-17 20:54:58 +0200 |
| commit | dce037a62c5bda9a8256d271d39b06be366120e8 (patch) | |
| tree | 67d022cbceb487f5359215d7c9ca51959100f549 /techlibs/quicklogic/Makefile.inc | |
| parent | a58571d0fe8971cb7d3a619a31b2c21be6d75bac (diff) | |
| download | yosys-dce037a62c5bda9a8256d271d39b06be366120e8.tar.gz yosys-dce037a62c5bda9a8256d271d39b06be366120e8.tar.bz2 yosys-dce037a62c5bda9a8256d271d39b06be366120e8.zip | |
quicklogic: ABC9 synthesis
Diffstat (limited to 'techlibs/quicklogic/Makefile.inc')
| -rw-r--r-- | techlibs/quicklogic/Makefile.inc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/techlibs/quicklogic/Makefile.inc b/techlibs/quicklogic/Makefile.inc index 9a07c2eed..51eb28d44 100644 --- a/techlibs/quicklogic/Makefile.inc +++ b/techlibs/quicklogic/Makefile.inc @@ -7,3 +7,7 @@ $(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_cells_map. $(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/cells_sim.v)) $(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/lut_sim.v)) $(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_cells_sim.v)) + +$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/abc9_model.v)) +$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/abc9_map.v)) +$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/abc9_unmap.v)) |