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| author | Miodrag Milanovic <mmicko@gmail.com> | 2023-03-31 15:46:35 +0200 |
|---|---|---|
| committer | myrtle <gatecat@ds0.me> | 2023-04-06 09:10:14 +0200 |
| commit | 6e4c1675e725983da8a11be0eda0b2de47a9f522 (patch) | |
| tree | 46203b164bdb889684ea51905c428f8783ca87e9 /techlibs/machxo2/lutrams_map.v | |
| parent | 6e12da3956a1960ce62ba389b10f02ef21a43291 (diff) | |
| download | yosys-6e4c1675e725983da8a11be0eda0b2de47a9f522.tar.gz yosys-6e4c1675e725983da8a11be0eda0b2de47a9f522.tar.bz2 yosys-6e4c1675e725983da8a11be0eda0b2de47a9f522.zip | |
Generate TRELLIS_DPR16X4 for lutram
Diffstat (limited to 'techlibs/machxo2/lutrams_map.v')
| -rw-r--r-- | techlibs/machxo2/lutrams_map.v | 43 |
1 files changed, 25 insertions, 18 deletions
diff --git a/techlibs/machxo2/lutrams_map.v b/techlibs/machxo2/lutrams_map.v index b55253fb8..3cb325f04 100644 --- a/techlibs/machxo2/lutrams_map.v +++ b/techlibs/machxo2/lutrams_map.v @@ -1,23 +1,30 @@ -module $__DPR16X4C_ (...); - parameter INIT = 64'b0; +module $__TRELLIS_DPR16X4_(...); - input PORT_W_CLK; - input [3:0] PORT_W_ADDR; - input [3:0] PORT_W_WR_DATA; - input PORT_W_WR_EN; +parameter INIT = 64'bx; +parameter PORT_W_CLK_POL = 1; - input [3:0] PORT_R_ADDR; - output [3:0] PORT_R_RD_DATA; +input PORT_W_CLK; +input [3:0] PORT_W_ADDR; +input [3:0] PORT_W_WR_DATA; +input PORT_W_WR_EN; - DPR16X4C #( - .INITVAL($sformatf("0x%08x", INIT)) - ) _TECHMAP_REPLACE_ ( - .RAD(PORT_R_ADDR), - .DO(PORT_R_RD_DATA), +input [3:0] PORT_R_ADDR; +output [3:0] PORT_R_RD_DATA; + +localparam WCKMUX = PORT_W_CLK_POL ? "WCK" : "INV"; + +TRELLIS_DPR16X4 #( + .INITVAL(INIT), + .WCKMUX(WCKMUX), + .WREMUX("WRE") +) _TECHMAP_REPLACE_ ( + .RAD(PORT_R_ADDR), + .DO(PORT_R_RD_DATA), + + .WAD(PORT_W_ADDR), + .DI(PORT_W_WR_DATA), + .WCK(PORT_W_CLK), + .WRE(PORT_W_WR_EN) +); - .WAD(PORT_W_ADDR), - .DI(PORT_W_WR_DATA), - .WCK(PORT_W_CLK), - .WRE(PORT_W_WR_EN) - ); endmodule |