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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2022-03-06 03:43:13 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2022-05-18 17:32:56 +0200 |
| commit | 2dcb0797f08c3747da5144c2940f71c03a39c9b6 (patch) | |
| tree | 706e23f0067b739441d5068bb60de7aa34258e7f /techlibs/machxo2/lutrams_map.v | |
| parent | 9d11575856e2345d2a6ae68f6b944d256d1e131a (diff) | |
| download | yosys-2dcb0797f08c3747da5144c2940f71c03a39c9b6.tar.gz yosys-2dcb0797f08c3747da5144c2940f71c03a39c9b6.tar.bz2 yosys-2dcb0797f08c3747da5144c2940f71c03a39c9b6.zip | |
machxo2: Use `memory_libmap` pass.
Diffstat (limited to 'techlibs/machxo2/lutrams_map.v')
| -rw-r--r-- | techlibs/machxo2/lutrams_map.v | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/techlibs/machxo2/lutrams_map.v b/techlibs/machxo2/lutrams_map.v new file mode 100644 index 000000000..b55253fb8 --- /dev/null +++ b/techlibs/machxo2/lutrams_map.v @@ -0,0 +1,23 @@ +module $__DPR16X4C_ (...); + parameter INIT = 64'b0; + + input PORT_W_CLK; + input [3:0] PORT_W_ADDR; + input [3:0] PORT_W_WR_DATA; + input PORT_W_WR_EN; + + input [3:0] PORT_R_ADDR; + output [3:0] PORT_R_RD_DATA; + + DPR16X4C #( + .INITVAL($sformatf("0x%08x", INIT)) + ) _TECHMAP_REPLACE_ ( + .RAD(PORT_R_ADDR), + .DO(PORT_R_RD_DATA), + + .WAD(PORT_W_ADDR), + .DI(PORT_W_WR_DATA), + .WCK(PORT_W_CLK), + .WRE(PORT_W_WR_EN) + ); +endmodule |