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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2022-03-06 03:43:13 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2022-05-18 17:32:56 +0200 |
| commit | 2dcb0797f08c3747da5144c2940f71c03a39c9b6 (patch) | |
| tree | 706e23f0067b739441d5068bb60de7aa34258e7f /techlibs/machxo2/lutrams.txt | |
| parent | 9d11575856e2345d2a6ae68f6b944d256d1e131a (diff) | |
| download | yosys-2dcb0797f08c3747da5144c2940f71c03a39c9b6.tar.gz yosys-2dcb0797f08c3747da5144c2940f71c03a39c9b6.tar.bz2 yosys-2dcb0797f08c3747da5144c2940f71c03a39c9b6.zip | |
machxo2: Use `memory_libmap` pass.
Diffstat (limited to 'techlibs/machxo2/lutrams.txt')
| -rw-r--r-- | techlibs/machxo2/lutrams.txt | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/techlibs/machxo2/lutrams.txt b/techlibs/machxo2/lutrams.txt new file mode 100644 index 000000000..c6b0b6c45 --- /dev/null +++ b/techlibs/machxo2/lutrams.txt @@ -0,0 +1,12 @@ +ram distributed $__DPR16X4C_ { + abits 4; + width 4; + cost 4; + init no_undef; + prune_rom; + port sw "W" { + clock posedge; + } + port ar "R" { + } +} |