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| author | Miodrag Milanovic <mmicko@gmail.com> | 2023-03-31 15:46:35 +0200 |
|---|---|---|
| committer | myrtle <gatecat@ds0.me> | 2023-04-06 09:10:14 +0200 |
| commit | 6e4c1675e725983da8a11be0eda0b2de47a9f522 (patch) | |
| tree | 46203b164bdb889684ea51905c428f8783ca87e9 /techlibs/machxo2/cells_sim.v | |
| parent | 6e12da3956a1960ce62ba389b10f02ef21a43291 (diff) | |
| download | yosys-6e4c1675e725983da8a11be0eda0b2de47a9f522.tar.gz yosys-6e4c1675e725983da8a11be0eda0b2de47a9f522.tar.bz2 yosys-6e4c1675e725983da8a11be0eda0b2de47a9f522.zip | |
Generate TRELLIS_DPR16X4 for lutram
Diffstat (limited to 'techlibs/machxo2/cells_sim.v')
| -rw-r--r-- | techlibs/machxo2/cells_sim.v | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/techlibs/machxo2/cells_sim.v b/techlibs/machxo2/cells_sim.v index f69c6d1e9..1e920329c 100644 --- a/techlibs/machxo2/cells_sim.v +++ b/techlibs/machxo2/cells_sim.v @@ -201,6 +201,50 @@ module DCMA ( endmodule (* abc9_box, lib_whitebox *) +module TRELLIS_DPR16X4 ( + input [3:0] DI, + input [3:0] WAD, + input WRE, + input WCK, + input [3:0] RAD, + output [3:0] DO +); + parameter WCKMUX = "WCK"; + parameter WREMUX = "WRE"; + parameter [63:0] INITVAL = 64'h0000000000000000; + + reg [3:0] mem[15:0]; + + integer i; + initial begin + for (i = 0; i < 16; i = i + 1) + mem[i] <= INITVAL[4*i +: 4]; + end + + wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK; + + reg muxwre; + always @(*) + case (WREMUX) + "1": muxwre = 1'b1; + "0": muxwre = 1'b0; + "INV": muxwre = ~WRE; + default: muxwre = WRE; + endcase + + always @(posedge muxwck) + if (muxwre) + mem[WAD] <= DI; + + assign DO = mem[RAD]; + + specify + // TODO + (RAD *> DO) = 0; + endspecify +endmodule + +(* abc9_box, lib_whitebox *) module DPR16X4C ( input [3:0] DI, input WCK, WRE, |