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author | Marcelina KoĆcielnicka <mwk@0x04.net> | 2022-03-06 03:43:13 +0100 |
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committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2022-05-18 17:32:56 +0200 |
commit | 2dcb0797f08c3747da5144c2940f71c03a39c9b6 (patch) | |
tree | 706e23f0067b739441d5068bb60de7aa34258e7f /techlibs/machxo2/brams.txt | |
parent | 9d11575856e2345d2a6ae68f6b944d256d1e131a (diff) | |
download | yosys-2dcb0797f08c3747da5144c2940f71c03a39c9b6.tar.gz yosys-2dcb0797f08c3747da5144c2940f71c03a39c9b6.tar.bz2 yosys-2dcb0797f08c3747da5144c2940f71c03a39c9b6.zip |
machxo2: Use `memory_libmap` pass.
Diffstat (limited to 'techlibs/machxo2/brams.txt')
-rw-r--r-- | techlibs/machxo2/brams.txt | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/techlibs/machxo2/brams.txt b/techlibs/machxo2/brams.txt new file mode 100644 index 000000000..3afbeda07 --- /dev/null +++ b/techlibs/machxo2/brams.txt @@ -0,0 +1,50 @@ +ram block $__DP8KC_ { + abits 13; + widths 1 2 4 9 per_port; + cost 64; + init no_undef; + port srsw "A" "B" { + clock posedge; + clken; + portoption "WRITEMODE" "NORMAL" { + rdwr no_change; + } + portoption "WRITEMODE" "WRITETHROUGH" { + rdwr new; + } + portoption "WRITEMODE" "READBEFOREWRITE" { + rdwr old; + } + option "RESETMODE" "SYNC" { + rdsrst zero ungated block_wr; + } + option "RESETMODE" "ASYNC" { + rdarst zero; + } + rdinit zero; + } +} + +ram block $__PDPW8KC_ { + abits 13; + widths 1 2 4 9 18 per_port; + byte 9; + cost 64; + init no_undef; + port sr "R" { + clock posedge; + clken; + option "RESETMODE" "SYNC" { + rdsrst zero ungated; + } + option "RESETMODE" "ASYNC" { + rdarst zero; + } + rdinit zero; + } + port sw "W" { + width 18; + clock posedge; + clken; + } +} |