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author | gatecat <gatecat@ds0.me> | 2021-05-15 14:34:48 +0100 |
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committer | gatecat <gatecat@ds0.me> | 2021-05-15 22:37:06 +0100 |
commit | eb106732d94322fb5b48fbff0420ce5a6fc83eb9 (patch) | |
tree | 3ed44e78ce74793b5d5625c04475641e6e977a33 /techlibs/intel_alm/common/mem_sim.v | |
parent | 5dba138c87762d4b5bb7b9348da372a92fab1cc0 (diff) | |
download | yosys-eb106732d94322fb5b48fbff0420ce5a6fc83eb9.tar.gz yosys-eb106732d94322fb5b48fbff0420ce5a6fc83eb9.tar.bz2 yosys-eb106732d94322fb5b48fbff0420ce5a6fc83eb9.zip |
intel_alm: Add global buffer insertion
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'techlibs/intel_alm/common/mem_sim.v')
-rw-r--r-- | techlibs/intel_alm/common/mem_sim.v | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/techlibs/intel_alm/common/mem_sim.v b/techlibs/intel_alm/common/mem_sim.v index e09aafaa2..dbdf69839 100644 --- a/techlibs/intel_alm/common/mem_sim.v +++ b/techlibs/intel_alm/common/mem_sim.v @@ -50,7 +50,9 @@ // model can be treated as always returning a defined result. (* abc9_box, lib_whitebox *) -module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1ADDR, output B1DATA); +module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, + (* clkbuf_sink *) input CLK1, + input [4:0] B1ADDR, output B1DATA); reg [31:0] mem = 32'b0; @@ -83,7 +85,7 @@ module MISTRAL_M10K(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); parameter CFG_ABITS = 10; parameter CFG_DBITS = 10; -input CLK1; +(* clkbuf_sink *) input CLK1; input [CFG_ABITS-1:0] A1ADDR, B1ADDR; input [CFG_DBITS-1:0] A1DATA; input A1EN, B1EN; |