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author | Dan Ravensloft <dan.ravensloft@gmail.com> | 2020-06-11 22:25:04 +0100 |
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committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2020-07-05 23:28:59 +0200 |
commit | 09ecb9b2cf3ab76841d30712bf70dafc6d47ef67 (patch) | |
tree | 11db41357b31c25744d10ef150ce2efda94bd42d /techlibs/intel_alm/common/megafunction_bb.v | |
parent | af54b8bc6123f6e90a97268624b84ac270dc1879 (diff) | |
download | yosys-09ecb9b2cf3ab76841d30712bf70dafc6d47ef67.tar.gz yosys-09ecb9b2cf3ab76841d30712bf70dafc6d47ef67.tar.bz2 yosys-09ecb9b2cf3ab76841d30712bf70dafc6d47ef67.zip |
intel_alm: direct M10K instantiation
Diffstat (limited to 'techlibs/intel_alm/common/megafunction_bb.v')
-rw-r--r-- | techlibs/intel_alm/common/megafunction_bb.v | 37 |
1 files changed, 36 insertions, 1 deletions
diff --git a/techlibs/intel_alm/common/megafunction_bb.v b/techlibs/intel_alm/common/megafunction_bb.v index b5a3d8892..820b0430e 100644 --- a/techlibs/intel_alm/common/megafunction_bb.v +++ b/techlibs/intel_alm/common/megafunction_bb.v @@ -156,4 +156,39 @@ input [ax_width-1:0] ax; input [ay_scan_in_width-1:0] ay; output [result_a_width-1:0] resulta; -endmodule
\ No newline at end of file +endmodule + +(* blackbox *) +module cyclonev_ram_block(portaaddr, portadatain, portawe, portbaddr, portbdataout, portbre, clk0); + +parameter operation_mode = "dual_port"; +parameter logical_ram_name = ""; +parameter port_a_address_width = 10; +parameter port_a_data_width = 10; +parameter port_a_logical_ram_depth = 1024; +parameter port_a_logical_ram_width = 10; +parameter port_a_first_address = 0; +parameter port_a_last_address = 1023; +parameter port_a_first_bit_number = 0; +parameter port_b_address_width = 10; +parameter port_b_data_width = 10; +parameter port_b_logical_ram_depth = 1024; +parameter port_b_logical_ram_width = 10; +parameter port_b_first_address = 0; +parameter port_b_last_address = 1023; +parameter port_b_first_bit_number = 0; +parameter port_b_address_clock = "clock0"; +parameter port_b_read_enable_clock = "clock0"; +parameter mem_init0 = ""; +parameter mem_init1 = ""; +parameter mem_init2 = ""; +parameter mem_init3 = ""; +parameter mem_init4 = ""; + +input [port_a_address_width-1:0] portaaddr; +input [port_b_address_width-1:0] portbaddr; +input [port_a_data_width-1:0] portadatain; +output [port_b_data_width-1:0] portbdataout; +input clk0, portawe, portbre; + +endmodule |