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| author | Dan Ravensloft <dan.ravensloft@gmail.com> | 2020-07-21 13:58:38 +0100 |
|---|---|---|
| committer | Dan Ravensloft <dan.ravensloft@gmail.com> | 2020-07-23 11:57:07 +0100 |
| commit | 4d9d90079c6e069fcba7ce04e8005285f4f237fe (patch) | |
| tree | a9f6ef195c0fe55d298095f36af349ae23a7da3e /techlibs/intel_alm/common/dsp_sim.v | |
| parent | eed05953f820439178b2138cef7d53d50528354a (diff) | |
| download | yosys-4d9d90079c6e069fcba7ce04e8005285f4f237fe.tar.gz yosys-4d9d90079c6e069fcba7ce04e8005285f4f237fe.tar.bz2 yosys-4d9d90079c6e069fcba7ce04e8005285f4f237fe.zip | |
intel_alm: add additional ABC9 timings
Diffstat (limited to 'techlibs/intel_alm/common/dsp_sim.v')
| -rw-r--r-- | techlibs/intel_alm/common/dsp_sim.v | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/techlibs/intel_alm/common/dsp_sim.v b/techlibs/intel_alm/common/dsp_sim.v index 5dc4c02de..7e72dab0d 100644 --- a/techlibs/intel_alm/common/dsp_sim.v +++ b/techlibs/intel_alm/common/dsp_sim.v @@ -1,9 +1,10 @@ (* abc9_box *) module MISTRAL_MUL27x27(input [26:0] A, input [26:0] B, output [53:0] Y); +// TODO: Cyclone 10 GX timings; the below are for Cyclone V specify - (A *> Y) = 4057; - (B *> Y) = 4057; + (A *> Y) = 3732; + (B *> Y) = 3928; endspecify assign Y = $signed(A) * $signed(B); @@ -13,9 +14,10 @@ endmodule (* abc9_box *) module MISTRAL_MUL18X18(input [17:0] A, input [17:0] B, output [35:0] Y); +// TODO: Cyclone 10 GX timings; the below are for Cyclone V specify - (A *> Y) = 4057; - (B *> Y) = 4057; + (A *> Y) = 3180; + (B *> Y) = 3982; endspecify assign Y = $signed(A) * $signed(B); @@ -25,9 +27,10 @@ endmodule (* abc9_box *) module MISTRAL_MUL9X9(input [8:0] A, input [8:0] B, output [17:0] Y); +// TODO: Cyclone 10 GX timings; the below are for Cyclone V specify - (A *> Y) = 4057; - (B *> Y) = 4057; + (A *> Y) = 2818; + (B *> Y) = 3051; endspecify assign Y = $signed(A) * $signed(B); |