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| author | Lofty <dan.ravensloft@gmail.com> | 2021-11-24 21:20:40 +0000 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-11-25 17:20:36 +0100 |
| commit | a31c8a82be4ec98dbe58ce7efdde3a372b9767e0 (patch) | |
| tree | fb291eb084201f1f1669e36cb6533b9adb43d101 /techlibs/intel_alm/common/alm_sim.v | |
| parent | 77327b2544a30b15e8efc79e1f62661ff25d306c (diff) | |
| download | yosys-a31c8a82be4ec98dbe58ce7efdde3a372b9767e0.tar.gz yosys-a31c8a82be4ec98dbe58ce7efdde3a372b9767e0.tar.bz2 yosys-a31c8a82be4ec98dbe58ce7efdde3a372b9767e0.zip | |
intel_alm: preliminary Arria V support
Diffstat (limited to 'techlibs/intel_alm/common/alm_sim.v')
| -rw-r--r-- | techlibs/intel_alm/common/alm_sim.v | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/techlibs/intel_alm/common/alm_sim.v b/techlibs/intel_alm/common/alm_sim.v index 6e70be865..242f1003f 100644 --- a/techlibs/intel_alm/common/alm_sim.v +++ b/techlibs/intel_alm/common/alm_sim.v @@ -77,6 +77,14 @@ // SUMOUT 368 1342 1323 887 927 - 785 - // CARRYOUT 71 1082 1062 866 813 - 1198 - +// Arria V LUT output timings (picoseconds): +// +// CARRY A B C D E F G +// COMBOUT - 387 375 316 317 - 76 319 (LUT6) +// COMBOUT - 387 375 316 317 218 76 319 (LUT7) +// SUMOUT 249 744 732 562 576 - 511 - +// CARRYOUT 19 629 623 530 514 - 696 - + (* abc9_lut=2, lib_whitebox *) module MISTRAL_ALUT6(input A, B, C, D, E, F, output Q); @@ -92,6 +100,16 @@ specify (F => Q) = 97; endspecify `endif +`ifdef arriav +specify + (A => Q) = 387; + (B => Q) = 375; + (C => Q) = 316; + (D => Q) = 317; + (E => Q) = 319; + (F => Q) = 76; +endspecify +`endif `ifdef cyclone10gx specify (A => Q) = 275; @@ -122,6 +140,15 @@ specify (E => Q) = 97; endspecify `endif +`ifdef arriav +specify + (A => Q) = 375; + (B => Q) = 316; + (C => Q) = 317; + (D => Q) = 319; + (E => Q) = 76; +endspecify +`endif `ifdef cyclone10gx specify (A => Q) = 272; @@ -150,6 +177,14 @@ specify (D => Q) = 97; endspecify `endif +`ifdef arriav +specify + (A => Q) = 316; + (B => Q) = 317; + (C => Q) = 319; + (D => Q) = 76; +endspecify +`endif `ifdef cyclone10gx specify (A => Q) = 175; @@ -176,6 +211,13 @@ specify (C => Q) = 97; endspecify `endif +`ifdef arriav +specify + (A => Q) = 316; + (B => Q) = 317; + (C => Q) = 76; +endspecify +`endif `ifdef cyclone10gx specify (A => Q) = 165; @@ -200,6 +242,12 @@ specify (B => Q) = 97; endspecify `endif +`ifdef arriav +specify + (A => Q) = 316; + (B => Q) = 76; +endspecify +`endif `ifdef cyclone10gx specify (A => Q) = 162; @@ -220,6 +268,11 @@ specify (A => Q) = 97; endspecify `endif +`ifdef arriav +specify + (A => Q) = 76; +endspecify +`endif `ifdef cyclone10gx specify (A => Q) = 53; @@ -255,6 +308,23 @@ specify (CI => CO) = 36; // Divided by 2 to account for there being two ALUT_ARITHs in an ALM) endspecify `endif +`ifdef arriav +specify + (A => SO) = 744; + (B => SO) = 732; + (C => SO) = 562; + (D0 => SO) = 576; + (D1 => SO) = 511; + (CI => SO) = 249; + + (A => CO) = 629; + (B => CO) = 623; + (C => CO) = 530; + (D0 => CO) = 514; + (D1 => CO) = 696; + (CI => CO) = 10; // Divided by 2 to account for there being two ALUT_ARITHs in an ALM) +endspecify +`endif `ifdef cyclone10gx specify (A => SO) = 644; |