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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-25 15:15:20 -0700 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-04 19:45:10 +0200 |
| commit | 3db3e1e1491b426766f1da87e1da840f3fa46278 (patch) | |
| tree | 67eba12a29a5ef77dfac113e6a148d9be92a93cc /techlibs/intel_alm/common/abc9_model.v | |
| parent | 83cde2d02ba06bbd4014858983ac324bf44cb6c6 (diff) | |
| download | yosys-3db3e1e1491b426766f1da87e1da840f3fa46278.tar.gz yosys-3db3e1e1491b426766f1da87e1da840f3fa46278.tar.bz2 yosys-3db3e1e1491b426766f1da87e1da840f3fa46278.zip | |
intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLY
Diffstat (limited to 'techlibs/intel_alm/common/abc9_model.v')
| -rw-r--r-- | techlibs/intel_alm/common/abc9_model.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/intel_alm/common/abc9_model.v b/techlibs/intel_alm/common/abc9_model.v index dd46147a5..8ad52e13a 100644 --- a/techlibs/intel_alm/common/abc9_model.v +++ b/techlibs/intel_alm/common/abc9_model.v @@ -18,7 +18,7 @@ // This is a purely-synchronous flop, that ABC9 can use for sequential synthesis. (* abc9_flop, lib_whitebox *) -module MISTRAL_FF_SYNCONLY( +module $__MISTRAL_FF_SYNCONLY ( input DATAIN, CLK, ENA, SCLR, SLOAD, SDATA, output reg Q ); |