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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-23 09:56:58 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-07-23 09:56:58 -0700 |
| commit | a66f17b6a78af8f6989235f0c72d5548b0560a58 (patch) | |
| tree | ad135d83bf75e72b65e3136b4f6746c1f9cafab3 /techlibs/intel | |
| parent | be3d9c8eaac637d9fe11f750e163680639543fdd (diff) | |
| parent | 80884d6f7bd10d79e89ad3893ae557aa64af9742 (diff) | |
| download | yosys-a66f17b6a78af8f6989235f0c72d5548b0560a58.tar.gz yosys-a66f17b6a78af8f6989235f0c72d5548b0560a58.tar.bz2 yosys-a66f17b6a78af8f6989235f0c72d5548b0560a58.zip | |
Merge pull request #1212 from YosysHQ/eddie/signed_ice40_dsp
ice40: Fix SB_MAC16 sim model for signed modes
Diffstat (limited to 'techlibs/intel')
0 files changed, 0 insertions, 0 deletions