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author | KrystalDelusion <krystinedawn@yosyshq.com> | 2022-08-24 10:28:27 +1200 |
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committer | KrystalDelusion <krystinedawn@yosyshq.com> | 2022-08-24 10:40:57 +1200 |
commit | 9465b2af95a146f514fc1e0b2d31bc3d9a233fb7 (patch) | |
tree | 59001b194c2f573674c37352733427a3ec28a1c1 /techlibs/intel | |
parent | 029c2785e810fda0ccc5abbb6057af760f2fc6f3 (diff) | |
download | yosys-9465b2af95a146f514fc1e0b2d31bc3d9a233fb7.tar.gz yosys-9465b2af95a146f514fc1e0b2d31bc3d9a233fb7.tar.bz2 yosys-9465b2af95a146f514fc1e0b2d31bc3d9a233fb7.zip |
Fitting help messages to 80 character width
Uses the regex below to search (using vscode):
^\t\tlog\("(.{10,}(?<!\\n)|.{81,}\\n)"\);
Finds any log messages double indented (which help messages are)
and checks if *either* there are is no newline character at the end,
*or* the number of characters before the newline is more than 80.
Diffstat (limited to 'techlibs/intel')
-rw-r--r-- | techlibs/intel/synth_intel.cc | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 166c81843..e9594e6d8 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -39,21 +39,22 @@ struct SynthIntelPass : public ScriptPass { log(" -family <max10 | cyclone10lp | cycloneiv | cycloneive>\n"); log(" generate the synthesis netlist for the specified family.\n"); log(" MAX10 is the default target if no family argument specified.\n"); - log(" For Cyclone IV GX devices, use cycloneiv argument; for Cyclone IV E, use cycloneive.\n"); - log(" For Cyclone V and Cyclone 10 GX, use the synth_intel_alm backend instead.\n"); + log(" For Cyclone IV GX devices, use cycloneiv argument; for Cyclone IV E, use\n"); + log(" cycloneive. For Cyclone V and Cyclone 10 GX, use the synth_intel_alm\n"); + log(" backend instead.\n"); log("\n"); log(" -top <module>\n"); log(" use the specified module as top module (default='top')\n"); log("\n"); log(" -vqm <file>\n"); - log(" write the design to the specified Verilog Quartus Mapping File. Writing of an\n"); - log(" output file is omitted if this parameter is not specified.\n"); + log(" write the design to the specified Verilog Quartus Mapping File. Writing\n"); + log(" of an output file is omitted if this parameter is not specified.\n"); log(" Note that this backend has not been tested and is likely incompatible\n"); log(" with recent versions of Quartus.\n"); log("\n"); log(" -vpr <file>\n"); - log(" write BLIF files for VPR flow experiments. The synthesized BLIF output file is not\n"); - log(" compatible with the Quartus flow. Writing of an\n"); + log(" write BLIF files for VPR flow experiments. The synthesized BLIF output\n"); + log(" file is not compatible with the Quartus flow. Writing of an\n"); log(" output file is omitted if this parameter is not specified.\n"); log("\n"); log(" -run <from_label>:<to_label>\n"); |