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| author | David Shah <dave@ds0.me> | 2019-12-11 08:46:10 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-12-11 08:46:10 +0000 |
| commit | 613334d9dcb5c190de8396ff38e2ae73259aa7bf (patch) | |
| tree | 2cd1d71738c00c292a39718ecb241389207d8ebb /techlibs/intel/synth_intel.cc | |
| parent | 7e5602ad17b20f14e56fc4c64198ca2d576917df (diff) | |
| parent | 85a14895ca31ec8c34bf5c296a5740a798b06693 (diff) | |
| download | yosys-613334d9dcb5c190de8396ff38e2ae73259aa7bf.tar.gz yosys-613334d9dcb5c190de8396ff38e2ae73259aa7bf.tar.bz2 yosys-613334d9dcb5c190de8396ff38e2ae73259aa7bf.zip | |
Merge pull request #1564 from ZirconiumX/intel_housekeeping
Intel housekeeping
Diffstat (limited to 'techlibs/intel/synth_intel.cc')
| -rw-r--r-- | techlibs/intel/synth_intel.cc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index e5dc1adc7..c8c690e45 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -36,10 +36,10 @@ struct SynthIntelPass : public ScriptPass { log("\n"); log("This command runs synthesis for Intel FPGAs.\n"); log("\n"); - log(" -family < max10 | a10gx | cyclone10 | cyclonev | cycloneiv | cycloneive>\n"); + log(" -family <max10 | arria10gx | cyclone10lp | cyclonev | cycloneiv | cycloneive>\n"); log(" generate the synthesis netlist for the specified family.\n"); log(" MAX10 is the default target if no family argument specified.\n"); - log(" For Cyclone GX devices, use cycloneiv argument; For Cyclone E, use cycloneive.\n"); + log(" For Cyclone IV GX devices, use cycloneiv argument; for Cyclone IV E, use cycloneive.\n"); log(" Cyclone V and Arria 10 GX devices are experimental.\n"); log("\n"); log(" -top <module>\n"); @@ -148,11 +148,11 @@ struct SynthIntelPass : public ScriptPass { if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); if (family_opt != "max10" && - family_opt != "a10gx" && + family_opt != "arria10gx" && family_opt != "cyclonev" && family_opt != "cycloneiv" && family_opt != "cycloneive" && - family_opt != "cyclone10") + family_opt != "cyclone10lp") log_cmd_error("Invalid or no family specified: '%s'\n", family_opt.c_str()); log_header(design, "Executing SYNTH_INTEL pass.\n"); @@ -214,7 +214,7 @@ struct SynthIntelPass : public ScriptPass { } if (check_label("map_luts")) { - if (family_opt == "a10gx" || family_opt == "cyclonev") + if (family_opt == "arria10gx" || family_opt == "cyclonev") run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : "")); else run("abc -lut 4" + string(retime ? " -dff" : "")); |