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author | Eddie Hung <eddie@fpgeh.com> | 2019-12-12 14:56:15 -0800 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-12 14:56:15 -0800 |
commit | 3eed8835b5911c4c635e0cade0978987c09c7ab5 (patch) | |
tree | d78ca8c869ea101d7dd31b5db3ed52379e45af9a /techlibs/intel/synth_intel.cc | |
parent | 49c2e59b2a4fce770bdaa74177adff0ee995f90d (diff) | |
download | yosys-3eed8835b5911c4c635e0cade0978987c09c7ab5.tar.gz yosys-3eed8835b5911c4c635e0cade0978987c09c7ab5.tar.bz2 yosys-3eed8835b5911c4c635e0cade0978987c09c7ab5.zip |
abc9_map.v: fix Xilinx LUTRAM
Diffstat (limited to 'techlibs/intel/synth_intel.cc')
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