aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/intel/synth_intel.cc
diff options
context:
space:
mode:
authorClifford Wolf <clifford@clifford.at>2017-10-10 15:16:45 +0200
committerClifford Wolf <clifford@clifford.at>2017-10-10 15:16:45 +0200
commit12c10892e6783e0a1ef52776c232dd342745543f (patch)
tree52482dfe8d609403b743698116e889599a5f19db /techlibs/intel/synth_intel.cc
parentc10e96c9ec8c4e56935ba796af0fa3d1f22b2a71 (diff)
parent7c57d8fbb44cdc466f4e384528109ada7e52b4c1 (diff)
downloadyosys-12c10892e6783e0a1ef52776c232dd342745543f.tar.gz
yosys-12c10892e6783e0a1ef52776c232dd342745543f.tar.bz2
yosys-12c10892e6783e0a1ef52776c232dd342745543f.zip
Merge branch 'master' of github.com:cliffordwolf/yosys
Diffstat (limited to 'techlibs/intel/synth_intel.cc')
-rw-r--r--[-rwxr-xr-x]techlibs/intel/synth_intel.cc6
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc
index 5f8b9c92a..9e4b33601 100755..100644
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc
@@ -170,7 +170,7 @@ struct SynthIntelPass : public ScriptPass {
{
run("synth -run coarse");
}
-
+
if (!nobram && check_label("bram", "(skip if -nobram)"))
{
run("memory_bram -rules +/intel/common/brams.txt");
@@ -179,7 +179,7 @@ struct SynthIntelPass : public ScriptPass {
if (check_label("fine"))
{
- run("opt -fast -mux_undef -undriven -fine -full");
+ run("opt -fast -mux_undef -undriven -fine -full");
run("memory_map");
run("opt -undriven -fine");
run("dffsr2dff");
@@ -209,7 +209,7 @@ struct SynthIntelPass : public ScriptPass {
run("techmap -map +/intel/max10/cells_map.v");
else if(family_opt=="a10gx")
run("techmap -map +/intel/a10gx/cells_map.v");
- else if(family_opt=="cyclonev")
+ else if(family_opt=="cyclonev")
run("techmap -map +/intel/cyclonev/cells_map.v");
else if(family_opt=="cycloneiv")
run("techmap -map +/intel/cycloneiv/cells_map.v");