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| author | N. Engelhardt <nak@symbioticeda.com> | 2020-06-05 11:36:08 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-06-05 11:36:08 +0200 |
| commit | 9669e0c7d50601263345d20fcbdb6a1b2001efc1 (patch) | |
| tree | 82d27383ffd140af29ed35da6609bb946cda0479 /techlibs/intel/max10/cells_sim.v | |
| parent | 7112f187cd5c8c34c7945132cb90d5a11fcfa554 (diff) | |
| parent | 82798ae57512fe410494821ca2d177116b3a3c63 (diff) | |
| download | yosys-9669e0c7d50601263345d20fcbdb6a1b2001efc1.tar.gz yosys-9669e0c7d50601263345d20fcbdb6a1b2001efc1.tar.bz2 yosys-9669e0c7d50601263345d20fcbdb6a1b2001efc1.zip | |
Merge pull request #2109 from nakengelhardt/btor_internal_names
btor backend: make not printing internal names default
Diffstat (limited to 'techlibs/intel/max10/cells_sim.v')
0 files changed, 0 insertions, 0 deletions