diff options
author | Marcelina KoĆcielnicka <mwk@0x04.net> | 2020-05-18 18:15:03 +0200 |
---|---|---|
committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2020-05-19 01:42:40 +0200 |
commit | aee439360bba642dcbffe5b803aa9a994b11d183 (patch) | |
tree | a5c15b4a6172ea3ff651f88174fff7d5269ad1c2 /techlibs/intel/max10/cells_map.v | |
parent | 2d573a0ff680eb9f38358943fbf134f765ba1451 (diff) | |
download | yosys-aee439360bba642dcbffe5b803aa9a994b11d183.tar.gz yosys-aee439360bba642dcbffe5b803aa9a994b11d183.tar.bz2 yosys-aee439360bba642dcbffe5b803aa9a994b11d183.zip |
Add force_downto and force_upto wire attributes.
Fixes #2058.
Diffstat (limited to 'techlibs/intel/max10/cells_map.v')
-rw-r--r-- | techlibs/intel/max10/cells_map.v | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/techlibs/intel/max10/cells_map.v b/techlibs/intel/max10/cells_map.v index 6d604e072..6a4072049 100644 --- a/techlibs/intel/max10/cells_map.v +++ b/techlibs/intel/max10/cells_map.v @@ -71,6 +71,7 @@ endmodule module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; + (* force_downto *) input [WIDTH-1:0] A; output Y; generate |