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| author | David Shah <davey1576@gmail.com> | 2018-12-07 17:17:26 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-12-07 17:17:26 +0000 |
| commit | 435776120a40ed06ea42ca63bcca231913507ac3 (patch) | |
| tree | 1509de1bf1e0413a23f48aaf066a69ea9068cb8f /techlibs/intel/max10/cells_map.v | |
| parent | 7d1088afc453f57f0ecc0f55ac2c91fd72ad8f2e (diff) | |
| parent | 7ec740b7ad4ee4bc02e2564671e0153cdd08152f (diff) | |
| download | yosys-435776120a40ed06ea42ca63bcca231913507ac3.tar.gz yosys-435776120a40ed06ea42ca63bcca231913507ac3.tar.bz2 yosys-435776120a40ed06ea42ca63bcca231913507ac3.zip | |
Merge pull request #727 from whitequark/opt_lut
opt_lut: leave intact LUTs with cascade feeding module outputs
Diffstat (limited to 'techlibs/intel/max10/cells_map.v')
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