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authorwhitequark <whitequark@whitequark.org>2021-02-04 09:57:28 +0000
committerGitHub <noreply@github.com>2021-02-04 09:57:28 +0000
commitbaf1875307f1608762169d3037ba005da88b201e (patch)
tree44b84ab2ef42251cdc916a417e105c3f172c2a19 /techlibs/intel/max10/cells_arith.v
parentafcc31ceba35d33fc11f9e1592956bb4112ca0e3 (diff)
parentfe74b0cd95267bc78953236311382653a6db7f60 (diff)
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Merge pull request #2529 from zachjs/unnamed-genblk
verilog: significant block scoping improvements
Diffstat (limited to 'techlibs/intel/max10/cells_arith.v')
0 files changed, 0 insertions, 0 deletions
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/*
 *  yosys -- Yosys Open SYnthesis Suite
 *
 *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
 *
 *  Permission to use, copy, modify, and/or distribute this software for any
 *  purpose with or without fee is hereby granted, provided that the above
 *  copyright notice and this permission notice appear in all copies.
 *
 *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 */

#include "kernel/yosys.h"
#include "kernel/sigtools.h"

USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN

struct MemoryNordffPass : public Pass {
	MemoryNordffPass() : Pass("memory_nordff", "extract read port FFs from memories") { }
	void help() YS_OVERRIDE
	{
		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
		log("\n");
		log("    memory_nordff [options] [selection]\n");
		log("\n");
		log("This pass extracts FFs from memory read ports. This results in a netlist\n");