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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-11 17:16:46 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-11 17:16:46 -0700 |
| commit | f3081c20e7a9ac9b69581396999633272096b1e8 (patch) | |
| tree | 2ad99e2365eb8975c82fd6781633e16f81aedce4 /techlibs/intel/cyclonev | |
| parent | 4369fc17d03d5c1db84823a37ff0f56eb1477e8f (diff) | |
| download | yosys-f3081c20e7a9ac9b69581396999633272096b1e8.tar.gz yosys-f3081c20e7a9ac9b69581396999633272096b1e8.tar.bz2 yosys-f3081c20e7a9ac9b69581396999633272096b1e8.zip | |
Add support for A1 and B1 registers
Diffstat (limited to 'techlibs/intel/cyclonev')
0 files changed, 0 insertions, 0 deletions