Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now

3 files changed, 360 insertions, 0 deletions

diff --git a/techlibs/intel/cyclonev/cells_arith.v b/techlibs/intel/cyclonev/cells_arith.v
new file mode 100755
index 000000000..470b686bb
--- /dev/null
+++ b/techlibs/intel/cyclonev/cells_arith.v
@@ -0,0 +1,65 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+// NOTE: This is still WIP.
+(* techmap_celltype = "$alu" *)
+module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO);
+   parameter A_SIGNED = 0;
+   parameter B_SIGNED = 0;
+   parameter A_WIDTH  = 1;
+   parameter B_WIDTH  = 1;
+   parameter Y_WIDTH  = 1;
+
+	input [A_WIDTH-1:0] A;
+	input [B_WIDTH-1:0] B;
+	output [Y_WIDTH-1:0] X, Y;
+
+	input CI, BI;
+	//output [Y_WIDTH-1:0] CO;
+        output                 CO;
+
+	wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
+
+	wire [Y_WIDTH-1:0] A_buf, B_buf;
+	\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+	\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+	wire [Y_WIDTH-1:0] AA = A_buf;
+	wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
+	//wire [Y_WIDTH:0] C = {CO, CI};
+        wire [Y_WIDTH+1:0] COx;
+        wire [Y_WIDTH+1:0] C = {COx, CI};
+    
+	/* Start implementation */
+	(* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
+	
+	genvar i;
+	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
+	  if(i==Y_WIDTH-1) begin
+	    (* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b1111_0000_1110_0000), .sum_lutc_input("cin")) carry_end (.combout(COx[Y_WIDTH]), .dataa(1'b1), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[Y_WIDTH]));
+            assign CO = COx[Y_WIDTH];
+          end
+	  else
+	    fiftyfivenm_lcell_comb #(.lut_mask(16'b1001_0110_1110_1000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(COx[i+1]), .dataa(AA[i]), .datab(BB[i]), .datac(1'b1), .datad(1'b1), .cin(C[i+1]));
+	  end: slice
+	endgenerate
+	/* End implementation */
+	assign X = AA ^ BB;
+   
+endmodule  
diff --git a/techlibs/intel/cyclonev/cells_map.v b/techlibs/intel/cyclonev/cells_map.v
new file mode 100755
index 000000000..b3927ea4a
--- /dev/null
+++ b/techlibs/intel/cyclonev/cells_map.v
@@ -0,0 +1,151 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+// Normal mode DFF negedge clk, negedge reset
+module  \$_DFF_N_ (input D, C, output Q);
+   parameter WYSIWYG="TRUE";
+   dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
+endmodule
+// Normal mode DFF
+module  \$_DFF_P_ (input D, C, output Q);
+   parameter WYSIWYG="TRUE";
+   dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
+endmodule
+
+// Async Active Low Reset DFF
+module  \$_DFF_PN0_ (input D, C, R, output Q);
+   parameter WYSIWYG="TRUE";
+   dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
+endmodule
+// Async Active High Reset DFF
+module  \$_DFF_PP0_ (input D, C, R, output Q);
+   parameter WYSIWYG="TRUE";
+   wire R_i = ~ R;
+   dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
+endmodule
+
+module  \$__DFFE_PP0 (input D, C, E, R, output Q); 
+   parameter WYSIWYG="TRUE";
+   wire E_i = ~ E;
+   dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
+endmodule
+
+// Input buffer map
+module \$__inpad (input I, output O);
+   cyclonev_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
+endmodule
+
+// Output buffer map
+module \$__outpad (input I, output O);
+   cyclonev_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
+endmodule
+
+// LUT Map
+module \$lut (A, Y);
+   parameter WIDTH  = 0;
+   parameter LUT    = 0;
+   input [WIDTH-1:0] A;
+   output 	     Y;
+   generate
+      if (WIDTH == 1) begin
+	 assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
+      end 
+      else
+        if (WIDTH == 2) begin
+           cyclonev_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off")) 
+           _TECHMAP_REPLACE_ 
+             (.combout(Y), 
+              .dataa(A[0]), 
+              .datab(A[1]), 
+              .datac(1'b1),
+              .datad(1'b1), 
+              .datae(1'b1), 
+              .dataf(1'b1), 
+              .datag(1'b1));
+        end 
+        else
+          if(WIDTH == 3) begin
+	     cyclonev_lcell_comb #(.lut_mask({8{LUT}}), .shared_arith("off"), .extended_lut("off")) 
+             _TECHMAP_REPLACE_ 
+               (.combout(Y), 
+                .dataa(A[0]), 
+                .datab(A[1]), 
+                .datac(A[2]),
+                .datad(1'b1), 
+                .datae(1'b1), 
+                .dataf(1'b1), 
+                .datag(1'b1));
+          end 
+          else
+            if(WIDTH == 4) begin
+	       cyclonev_lcell_comb #(.lut_mask({4{LUT}}), .shared_arith("off"), .extended_lut("off")) 
+               _TECHMAP_REPLACE_ 
+                 (.combout(Y), 
+                  .dataa(A[0]), 
+                  .datab(A[1]), 
+                  .datac(A[2]),
+                  .datad(A[3]), 
+                  .datae(1'b1), 
+                  .dataf(1'b1), 
+                  .datag(1'b1));
+            end 
+            else
+              if(WIDTH == 5) begin 
+                 cyclonev_lcell_comb #(.lut_mask({2{LUT}}), .shared_arith("off"), .extended_lut("off"))
+                 _TECHMAP_REPLACE_ 
+                   (.combout(Y), 
+                    .dataa(A[0]), 
+                    .datab(A[1]), 
+                    .datac(A[2]),
+                    .datad(A[3]), 
+                    .datae(A[4]), 
+                    .dataf(1'b1), 
+                    .datag(1'b1));
+              end 
+              else
+                if(WIDTH == 6) begin
+                   cyclonev_lcell_comb #(.lut_mask(LUT), .shared_arith("off"), .extended_lut("off"))
+                   _TECHMAP_REPLACE_ 
+                     (.combout(Y), 
+                      .dataa(A[0]), 
+                      .datab(A[1]), 
+                      .datac(A[2]),
+                      .datad(A[3]), 
+                      .datae(A[4]), 
+                      .dataf(A[5]), 
+                      .datag(1'b1));
+                end 
+                else
+                  if(WIDTH == 7) begin
+                     cyclonev_lcell_comb #(.lut_mask(LUT), .shared_arith("off"), .extended_lut("off"))
+                     _TECHMAP_REPLACE_ 
+                       (.combout(Y), 
+                        .dataa(A[0]), 
+                        .datab(A[1]), 
+                        .datac(A[2]),
+                        .datad(A[3]), 
+                        .datae(A[4]), 
+                        .dataf(A[5]), 
+                        .datag(A[6]));
+                  end 
+                  else
+                     wire _TECHMAP_FAIL_ = 1;
+   endgenerate
+endmodule // lut
+
+
diff --git a/techlibs/intel/cyclonev/cells_sim.v b/techlibs/intel/cyclonev/cells_sim.v
new file mode 100755
index 000000000..363310e54
--- /dev/null
+++ b/techlibs/intel/cyclonev/cells_sim.v
@@ -0,0 +1,144 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+module VCC (output V);
+   assign V = 1'b1;
+endmodule // VCC
+
+module GND (output G);
+   assign G = 1'b0;
+endmodule // GND
+
+/* Altera Cyclone V devices Input Buffer Primitive */
+module cyclonev_io_ibuf 
+  (output o, input i, input ibar);
+   assign ibar = ibar;
+   assign o    = i;
+endmodule // cyclonev_io_ibuf
+
+/* Altera Cyclone V devices Output Buffer Primitive */
+module cyclonev_io_obuf 
+  (output o, input i, input oe);
+   assign o  = i;
+   assign oe = oe;
+endmodule // cyclonev_io_obuf
+
+/* Altera Cyclone V LUT Primitive */
+module cyclonev_lcell_comb 
+  (output combout, cout, sumout, shareout,
+   input dataa, datab, datac, datad, 
+   input datae, dataf, datag, cin,
+   input sharein);
+
+   parameter lut_mask      = 64'hFFFFFFFFFFFFFFFF;
+   parameter dont_touch    = "off";
+   parameter lpm_type      = "cyclonev_lcell_comb";
+   parameter shared_arith  = "off";
+   parameter extended_lut  = "off";
+
+   // Internal variables
+   // Sub mask for fragmented LUTs
+   wire [15:0] mask_a, mask_b, mask_c, mask_d;
+   // Independant output for fragmented LUTs
+   wire        output_0, output_1, output_2, output_3;
+   // Extended mode uses mux to define the output
+   wire        mux_0, mux_1;
+   // Input for hold the shared LUT mode value
+   wire        shared_lut_alm;        
+   
+   // Simulation model of 4-input LUT
+   function lut4;
+      input [15:0] mask;
+      input        dataa, datab, datac, datad;
+      reg [7:0]    s3;
+      reg [3:0]    s2;
+      reg [1:0]    s1;
+      begin
+         s3   = datad ? mask[15:8] : mask[7:0];
+         s2   = datac ?   s3[7:4]  :   s3[3:0];
+         s1   = datab ?   s2[3:2]  :   s2[1:0];
+         lut4 = dataa ? s1[1] : s1[0];
+      end
+   endfunction // lut4
+   
+   // Simulation model of 5-input LUT
+   function lut5;
+      input [31:0] mask; // wp-01003.pdf, page 3: "a 5-LUT can be built with two 4-LUTs and a multiplexer.
+      input        dataa, datab, datac, datad, datae;
+      reg          upper_lut_value;
+      reg          lower_lut_value;
+      begin
+         upper_lut_value = lut4(mask[31:16], dataa, datab, datac, datad);
+         lower_lut_value = lut4(mask[15:0], dataa, datab, datac, datad);
+         lut5            = (datae) ? upper_mask_value : lower_mask_value;
+      end
+   endfunction // lut5
+
+   // Simulation model of 6-input LUT
+   function lut6;
+      input [63:0] mask;
+      input        dataa, datab, datac, datad, datae, dataf;
+      reg          upper_lut_value;
+      reg          lower_lut_value;
+      begin
+         upper_lut_value = lut5(mask[63:32], dataa, datab, datac, datad, datae);
+         lower_lut_value = lut5(mask[31:0], dataa, datab, datac, datad, datae);
+         lut6            = (dataf) ?  upper_mask_value : lower_mask_value;
+      end
+   endfunction // lut6
+
+   assign {mask_a, mask_b, mask_c, mask_d} = {lut_mask[15:0], lut_mask[31:16], lut_mask[47:32], lut_mask[63:48]};
+
+   always @(*) begin
+      if(extended_lut == "on")
+        shared_lut_alm = datag;
+      else
+        shared_lut_alm = datac;
+      // Build the ALM behaviour
+      out_0 = lut4(mask_a, dataa, datab, datac, datad);
+      out_1 = lut4(mask_b, dataa, datab, shared_lut_alm, datad);
+      out_2 = lut4(mask_c, dataa, datab, datac, datad);
+      out_3 = lut4(mask_d, dataa, datab, shared_lut_alm, datad);
+   end
+endmodule // cyclonev_lcell_comb
+
+
+/* Altera D Flip-Flop Primitive */
+module dffeas 
+  (output q,
+   input d, clk, clrn, prn, ena,
+   input asdata, aload, sclr, sload);
+
+   // Timing simulation is not covered
+   parameter power_up="dontcare";
+   parameter is_wysiwyg="false";
+
+   reg   q_tmp;
+   wire  reset;
+   reg [7:0] debug_net;
+   
+   assign reset       = (prn && sclr && ~clrn && ena);
+   assign q           = q_tmp & 1'b1;
+
+   always @(posedge clk, posedge aload) begin
+      if(reset)        q_tmp <= 0;
+      else q_tmp <= d;
+   end
+   assign q = q_tmp;
+   
+endmodule // dffeas