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| author | whitequark <whitequark@whitequark.org> | 2020-06-10 11:51:04 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-06-10 11:51:04 +0000 |
| commit | 8f1a32064639fa17d67bda508df941c8846a0664 (patch) | |
| tree | f37eebf7b68c49248ac4966dce35449268de698e /techlibs/intel/cyclonev/cells_map.v | |
| parent | b2a0f49371170deb9c19bb9444c1c997fc1d1917 (diff) | |
| parent | 5467fe563a9b1d4db508f10b99e34e4d3fbf4675 (diff) | |
| download | yosys-8f1a32064639fa17d67bda508df941c8846a0664.tar.gz yosys-8f1a32064639fa17d67bda508df941c8846a0664.tar.bz2 yosys-8f1a32064639fa17d67bda508df941c8846a0664.zip | |
Merge pull request #2134 from whitequark/cxxrtl-opt-debug
cxxrtl: introduce -Og optimization level
Diffstat (limited to 'techlibs/intel/cyclonev/cells_map.v')
0 files changed, 0 insertions, 0 deletions