Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device

2 files changed, 65 insertions, 7 deletions

diff --git a/techlibs/intel/cycloneive/arith_map.v b/techlibs/intel/cycloneive/arith_map.v
index 634cec789..b3a11272b 100644
--- a/techlibs/intel/cycloneive/arith_map.v
+++ b/techlibs/intel/cycloneive/arith_map.v
@@ -16,6 +16,48 @@
  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  *
  */
+/* TODO: Describe the following mode */
+module fa
+  (input  a_c,
+   input  b_c,
+   input  cin_c,
+   output cout_t,
+   output sum_x);
+
+   wire   a_c;
+   wire   b_c;
+   wire   cout_t;
+   wire   cin_c;
+   wire   sum_x;
+   wire   VCC;
+
+   assign VCC = 1'b1;
+   
+   cycloneiv_lcell_comb gen_sum_0 (.combout(sum_x),
+                                   .dataa(a_c),
+                                   .datab(b_c),
+                                   .datac(cin_c),
+                                   .datad(VCC));
+   defparam syn__05_.lut_mask = 16'b1001011010010110;
+   defparam syn__05_.sum_lutc_input = "datac";
+   
+   cycloneiv_lcell_comb gen_cout_0 (.combout(cout_t),
+                                    .dataa(cin_c),
+                                    .datab(b_c),
+                                    .datac(a_c),
+                                    .datad(VCC));
+   defparam syn__06_.lut_mask = 16'b1110000011100000;
+   defparam syn__06_.sum_lutc_input = "datac";
+   
+endmodule // fa
+
+module f_stage();
+   
+endmodule // f_stage
+
+module f_end();
+
+endmodule // f_end
 
 module _80_cycloneive_alu (A, B, CI, BI, X, Y, CO);
    parameter A_SIGNED = 0;
@@ -41,8 +83,13 @@ module _80_cycloneive_alu (A, B, CI, BI, X, Y, CO);
    wire [Y_WIDTH-1:0]   BB = BI ? ~B_buf : B_buf;
    wire [Y_WIDTH:0]     C = {CO, CI};
 
-   cycloneive_lcell_comb #(.lut_mask(16'b0110_0110_1000_1000), .sum_lutc_input("cin")) carry_start  (.cout(CO[0]), .dataa(BB[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
-   genvar               i;
+   fa f0 (.a_c(AA[0]),
+          .b_c(BB[0]),
+          .cin_c(C[0]),
+          .cout_t(C0[1]),
+          .sum_x(Y[0]));
+   
+   genvar i;
    generate for (i = 1; i < Y_WIDTH; i = i + 1) begin:slice
       cycloneive_lcell_comb #(.lut_mask(16'b0101_1010_0101_0000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(CO[i]), .dataa(BB[i]), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[i]));
    end endgenerate
diff --git a/techlibs/intel/cycloneive/cells_map.v b/techlibs/intel/cycloneive/cells_map.v
index bf87f5525..abeb92eef 100644
--- a/techlibs/intel/cycloneive/cells_map.v
+++ b/techlibs/intel/cycloneive/cells_map.v
@@ -16,32 +16,43 @@
  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  *
  */
+// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
+// > Intel FPGA technology mapping. User must first simulate the generated \
+// > netlist before going to test it on board.
+// > Changelog: 1) The missing power_up parameter in the techmap introduces a problem in Quartus mapper. Fixed.
+
 // Normal mode DFF negedge clk, negedge reset
 module  \$_DFF_N_ (input D, C, output Q);
    parameter WYSIWYG="TRUE";
-   dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
+   parameter power_up=1'bx;
+   dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
 endmodule
 // Normal mode DFF
 module  \$_DFF_P_ (input D, C, output Q);
    parameter WYSIWYG="TRUE";
-   dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
+   parameter power_up=1'bx;
+   dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(1'b1), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
 endmodule
+
 // Async Active Low Reset DFF
 module  \$_DFF_PN0_ (input D, C, R, output Q);
    parameter WYSIWYG="TRUE";
-   dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
+   parameter power_up=1'bx;
+   dffeas #(.is_wysiwyg(WYSIWYG), .power_up("power_up")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
 endmodule
 // Async Active High Reset DFF
 module  \$_DFF_PP0_ (input D, C, R, output Q);
    parameter WYSIWYG="TRUE";
+   parameter power_up=1'bx;
    wire R_i = ~ R;
-   dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
+   dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
 endmodule
 
 module  \$__DFFE_PP0 (input D, C, E, R, output Q);
    parameter WYSIWYG="TRUE";
+   parameter power_up=1'bx;
    wire E_i = ~ E;
-   dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
+   dffeas #(.is_wysiwyg(WYSIWYG), .power_up(power_up)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
 endmodule
 
 // Input buffer map