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| author | Clifford Wolf <clifford@clifford.at> | 2019-07-02 11:36:26 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-07-02 11:36:26 +0200 |
| commit | d206eca03b8aa7bb982fb2486c02c90a61354066 (patch) | |
| tree | 076f2ecb015477a7f6783305ad901f14bf7950eb /techlibs/intel/cycloneive | |
| parent | 0067dc44f3928833eede2b9bb40260be78e11a93 (diff) | |
| download | yosys-d206eca03b8aa7bb982fb2486c02c90a61354066.tar.gz yosys-d206eca03b8aa7bb982fb2486c02c90a61354066.tar.bz2 yosys-d206eca03b8aa7bb982fb2486c02c90a61354066.zip | |
Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/SymbiYosys#53
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'techlibs/intel/cycloneive')
0 files changed, 0 insertions, 0 deletions