Add force_downto and force_upto wire attributes.

Fixes #2058.

2 files changed, 7 insertions, 0 deletions

diff --git a/techlibs/intel/cycloneive/arith_map.v b/techlibs/intel/cycloneive/arith_map.v
index 49e36aa25..a755e10db 100644
--- a/techlibs/intel/cycloneive/arith_map.v
+++ b/techlibs/intel/cycloneive/arith_map.v
@@ -66,8 +66,11 @@ module _80_cycloneive_alu (A, B, CI, BI, X, Y, CO);
    parameter B_WIDTH = 1;
    parameter Y_WIDTH = 1;
 
+   (* force_downto *)
    input [A_WIDTH-1:0] A;
+   (* force_downto *)
    input [B_WIDTH-1:0] B;
+   (* force_downto *)
    output [Y_WIDTH-1:0] X, Y;
 
    input                CI, BI;
@@ -75,11 +78,14 @@ module _80_cycloneive_alu (A, B, CI, BI, X, Y, CO);
 
    wire                 _TECHMAP_FAIL_ = Y_WIDTH < 5;
 
+   (* force_downto *)
    wire [Y_WIDTH-1:0]   A_buf, B_buf;
    \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
    \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
 
+   (* force_downto *)
    wire [Y_WIDTH-1:0]   AA = A_buf;
+   (* force_downto *)
    wire [Y_WIDTH-1:0]   BB = BI ? ~B_buf : B_buf;
    wire [Y_WIDTH:0]     C = {CO, CI};
 
diff --git a/techlibs/intel/cycloneive/cells_map.v b/techlibs/intel/cycloneive/cells_map.v
index abeb92eef..fead2837b 100644
--- a/techlibs/intel/cycloneive/cells_map.v
+++ b/techlibs/intel/cycloneive/cells_map.v
@@ -71,6 +71,7 @@ endmodule
 module \$lut (A, Y);
    parameter WIDTH  = 0;
    parameter LUT    = 0;
+   (* force_downto *)
    input [WIDTH-1:0] A;
    output            Y;
    generate