Clean whitespace and permissions in techlibs/intel

3 files changed, 32 insertions, 32 deletions

diff --git a/techlibs/intel/cycloneive/arith_map.v b/techlibs/intel/cycloneive/arith_map.v
index 3eaec3715..634cec789 100755..100644
--- a/techlibs/intel/cycloneive/arith_map.v
+++ b/techlibs/intel/cycloneive/arith_map.v
@@ -40,7 +40,7 @@ module _80_cycloneive_alu (A, B, CI, BI, X, Y, CO);
    wire [Y_WIDTH-1:0]   AA = A_buf;
    wire [Y_WIDTH-1:0]   BB = BI ? ~B_buf : B_buf;
    wire [Y_WIDTH:0]     C = {CO, CI};
-   
+
    cycloneive_lcell_comb #(.lut_mask(16'b0110_0110_1000_1000), .sum_lutc_input("cin")) carry_start  (.cout(CO[0]), .dataa(BB[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
    genvar               i;
    generate for (i = 1; i < Y_WIDTH; i = i + 1) begin:slice
@@ -48,5 +48,5 @@ module _80_cycloneive_alu (A, B, CI, BI, X, Y, CO);
    end endgenerate
 
    assign X = AA ^ BB;
-   
+
 endmodule
diff --git a/techlibs/intel/cycloneive/cells_map.v b/techlibs/intel/cycloneive/cells_map.v
index e7477773a..bf87f5525 100755..100644
--- a/techlibs/intel/cycloneive/cells_map.v
+++ b/techlibs/intel/cycloneive/cells_map.v
@@ -38,7 +38,7 @@ module  \$_DFF_PP0_ (input D, C, R, output Q);
    dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
 endmodule
 
-module  \$__DFFE_PP0 (input D, C, E, R, output Q); 
+module  \$__DFFE_PP0 (input D, C, E, R, output Q);
    parameter WYSIWYG="TRUE";
    wire E_i = ~ E;
    dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
@@ -61,38 +61,38 @@ module \$lut (A, Y);
    parameter WIDTH  = 0;
    parameter LUT    = 0;
    input [WIDTH-1:0] A;
-   output 	     Y;
+   output            Y;
    generate
       if (WIDTH == 1) begin
 	 assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
       end else
         if (WIDTH == 2) begin
-           cycloneive_lcell_comb #(.lut_mask({4{LUT}}), 
-                                   .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), 
-                                                                                .dataa(A[0]), 
-                                                                                .datab(A[1]), 
+           cycloneive_lcell_comb #(.lut_mask({4{LUT}}),
+                                   .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
+                                                                                .dataa(A[0]),
+                                                                                .datab(A[1]),
                                                                                 .datac(1'b1),
                                                                                 .datad(1'b1));
         end else
           if(WIDTH == 3) begin
-	     cycloneive_lcell_comb #(.lut_mask({2{LUT}}), 
-                                     .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), 
-                                                                                  .dataa(A[0]), 
-                                                                                  .datab(A[1]), 
+	     cycloneive_lcell_comb #(.lut_mask({2{LUT}}),
+                                     .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
+                                                                                  .dataa(A[0]),
+                                                                                  .datab(A[1]),
                                                                                   .datac(A[2]),
                                                                                   .datad(1'b1));
           end else
             if(WIDTH == 4) begin
-	       cycloneive_lcell_comb #(.lut_mask(LUT), 
-                                       .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), 
-                                                                                    .dataa(A[0]), 
-                                                                                    .datab(A[1]), 
+	       cycloneive_lcell_comb #(.lut_mask(LUT),
+                                       .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
+                                                                                    .dataa(A[0]),
+                                                                                    .datab(A[1]),
                                                                                     .datac(A[2]),
                                                                                     .datad(A[3]));
             end else
 	             wire _TECHMAP_FAIL_ = 1;
    endgenerate
-   
-endmodule 
+
+endmodule
 
 
diff --git a/techlibs/intel/cycloneive/cells_sim.v b/techlibs/intel/cycloneive/cells_sim.v
index 23d06bc1e..f17b86fdf 100755..100644
--- a/techlibs/intel/cycloneive/cells_sim.v
+++ b/techlibs/intel/cycloneive/cells_sim.v
@@ -25,21 +25,21 @@ module GND (output G);
 endmodule // GND
 
 /* Altera Cyclone IV (E) devices Input Buffer Primitive */
-module cycloneive_io_ibuf 
+module cycloneive_io_ibuf
   (output o, input i, input ibar);
    assign ibar = ibar;
    assign o    = i;
 endmodule // fiftyfivenm_io_ibuf
 
 /* Altera Cyclone IV (E)  devices Output Buffer Primitive */
-module cycloneive_io_obuf 
+module cycloneive_io_obuf
   (output o, input i, input oe);
    assign o  = i;
    assign oe = oe;
 endmodule // fiftyfivenm_io_obuf
 
 /* Altera Cyclone IV (E) 4-input non-fracturable LUT Primitive */
-module cycloneive_lcell_comb 
+module cycloneive_lcell_comb
   (output combout, cout,
    input dataa, datab, datac, datad, cin);
 
@@ -112,7 +112,7 @@ module cycloneive_lcell_comb
 endmodule // cycloneive_lcell_comb
 
 /* Altera D Flip-Flop Primitive */
-module dffeas 
+module dffeas
   (output q,
    input d, clk, clrn, prn, ena,
    input asdata, aload, sclr, sload);
@@ -124,7 +124,7 @@ module dffeas
    reg   q_tmp;
    wire  reset;
    reg [7:0] debug_net;
-   
+
    assign reset       = (prn && sclr && ~clrn && ena);
    assign q           = q_tmp & 1'b1;
 
@@ -133,7 +133,7 @@ module dffeas
       else q_tmp <= d;
    end
    assign q = q_tmp;
-   
+
 endmodule // dffeas
 
 /* Cyclone IV E altpll clearbox model */
@@ -174,9 +174,9 @@ module cycloneive_pll
    parameter bandwidth                     = 0;
    parameter bandwidth_type                = "auto";
    parameter use_dc_coupling               = "false";
-   parameter lock_high = 0; 
-   parameter lock_low = 0;  
-   parameter lock_window_ui                = "0.05"; 
+   parameter lock_high = 0;
+   parameter lock_low = 0;
+   parameter lock_window_ui                = "0.05";
    parameter test_bypass_lock_detect       = "off";
    parameter clk0_output_frequency         = 0;
    parameter clk0_multiply_by              = 0;
@@ -255,16 +255,16 @@ module cycloneive_pll
    parameter c4_test_source = -1;
    parameter vco_multiply_by = 0;
    parameter vco_divide_by = 0;
-   parameter vco_post_scale = 1; 
+   parameter vco_post_scale = 1;
    parameter vco_frequency_control = "auto";
    parameter vco_phase_shift_step = 0;
    parameter charge_pump_current = 10;
-   parameter loop_filter_r = "1.0";   
-   parameter loop_filter_c = 0;    
+   parameter loop_filter_r = "1.0";
+   parameter loop_filter_c = 0;
    parameter pll_compensation_delay = 0;
    parameter lpm_type = "cycloneive_pll";
    parameter phase_counter_select_width = 3;
- 
+
    input [1:0] inclk;
    input       fbin;
    input       clkswitch;
@@ -288,5 +288,5 @@ module cycloneive_pll
    output                                   phasedone;
    output                                   vcooverrange;
    output                                   vcounderrange;
-   
+
 endmodule // cycloneive_pll