Clean whitespace and permissions in techlibs/intel

3 files changed, 20 insertions, 20 deletions

diff --git a/techlibs/intel/cycloneiv/cells_arith.v b/techlibs/intel/cycloneiv/cells_arith.v
index 555b91599..010a4b5da 100755..100644
--- a/techlibs/intel/cycloneiv/cells_arith.v
+++ b/techlibs/intel/cycloneiv/cells_arith.v
@@ -19,7 +19,7 @@
 
 // NOTE: This is still WIP.
 (* techmap_celltype = "$alu" *)
-/* Uncomment this for LCU???? 
+/* Uncomment this for LCU????
 module _80_cycloneiv_alu (A, B, CI, BI, X, Y, CO);
 	parameter A_SIGNED = 0;
 	parameter B_SIGNED = 0;
@@ -46,7 +46,7 @@ module _80_cycloneiv_alu (A, B, CI, BI, X, Y, CO);
 	//wire [Y_WIDTH:0] C = {CO, CI};
         wire [Y_WIDTH+1:0] COx;
         wire [Y_WIDTH+1:0] C = {COx, CI};
-    
+
 	/* Start implementation */
 	//cycloneiv_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
 	/*
@@ -61,7 +61,7 @@ module _80_cycloneiv_alu (A, B, CI, BI, X, Y, CO);
 	endgenerate
 	/* End implementation */
 	/*assign X = AA ^ BB;
-   
+
 endmodule*/
 module _80_cycloneiv_alu (A, B, CI, BI, X, Y, CO);
         parameter A_SIGNED = 0;
@@ -86,7 +86,7 @@ module _80_cycloneiv_alu (A, B, CI, BI, X, Y, CO);
 	wire [Y_WIDTH-1:0] AA = A_buf;
 	wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
 	wire [Y_WIDTH:0] C = {CO, CI};
-        
+
         cycloneiv_lcell_comb #(.lut_mask(16'b0110_0110_1000_1000), .sum_lutc_input("cin")) carry_start  (.cout(CO[0]), .dataa(BB[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
 	genvar i;
 	generate for (i = 1; i < Y_WIDTH; i = i + 1) begin:slice
diff --git a/techlibs/intel/cycloneiv/cells_map.v b/techlibs/intel/cycloneiv/cells_map.v
index 4db91d926..b991fbae7 100755..100644
--- a/techlibs/intel/cycloneiv/cells_map.v
+++ b/techlibs/intel/cycloneiv/cells_map.v
@@ -39,7 +39,7 @@ module  \$_DFF_PP0_ (input D, C, R, output Q);
    dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
 endmodule
 
-module  \$__DFFE_PP0 (input D, C, E, R, output Q); 
+module  \$__DFFE_PP0 (input D, C, E, R, output Q);
    parameter WYSIWYG="TRUE";
    wire E_i = ~ E;
    dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
@@ -62,7 +62,7 @@ module \$lut (A, Y);
    parameter WIDTH  = 0;
    parameter LUT    = 0;
    input [WIDTH-1:0] A;
-   output 	     Y;
+   output            Y;
    generate
       if (WIDTH == 1) begin
 	   assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
diff --git a/techlibs/intel/cycloneiv/cells_sim.v b/techlibs/intel/cycloneiv/cells_sim.v
index a2891d6e4..2af2ab990 100755..100644
--- a/techlibs/intel/cycloneiv/cells_sim.v
+++ b/techlibs/intel/cycloneiv/cells_sim.v
@@ -26,7 +26,7 @@ module GND (output G);
 endmodule // GND
 
 /* Altera Cyclone IV (GX) devices Input Buffer Primitive */
-module cycloneiv_io_ibuf 
+module cycloneiv_io_ibuf
   (output o, input i, input ibar);
    assign ibar = ibar;
    assign o    = i;
@@ -40,7 +40,7 @@ module cycloneiv_io_obuf
 endmodule // fiftyfivenm_io_obuf
 
 /* Altera Cyclone IV (GX) 4-input non-fracturable LUT Primitive */
-module cycloneiv_lcell_comb 
+module cycloneiv_lcell_comb
   (output combout, cout,
    input dataa, datab, datac, datad, cin);
 
@@ -113,7 +113,7 @@ module cycloneiv_lcell_comb
 endmodule // cycloneiv_lcell_comb
 
 /* Altera D Flip-Flop Primitive */
-module dffeas 
+module dffeas
   (output q,
    input d, clk, clrn, prn, ena,
    input asdata, aload, sclr, sload);
@@ -125,7 +125,7 @@ module dffeas
    reg   q_tmp;
    wire  reset;
    reg [7:0] debug_net;
-   
+
    assign reset       = (prn && sclr && ~clrn && ena);
    assign q           = q_tmp & 1'b1;
 
@@ -134,7 +134,7 @@ module dffeas
       else q_tmp <= d;
    end
    assign q = q_tmp;
-   
+
 endmodule // dffeas
 
 /* Cyclone IV GX altpll clearbox model */
@@ -177,9 +177,9 @@ module cycloneiv_pll
    parameter bandwidth                     = 0;
    parameter bandwidth_type                = "auto";
    parameter use_dc_coupling               = "false";
-   parameter lock_high = 0; 
-   parameter lock_low = 0;  
-   parameter lock_window_ui                = "0.05"; 
+   parameter lock_high = 0;
+   parameter lock_low = 0;
+   parameter lock_window_ui                = "0.05";
    parameter test_bypass_lock_detect       = "off";
    parameter clk0_output_frequency         = 0;
    parameter clk0_multiply_by              = 0;
@@ -258,16 +258,16 @@ module cycloneiv_pll
    parameter c4_test_source = -1;
    parameter vco_multiply_by = 0;
    parameter vco_divide_by = 0;
-   parameter vco_post_scale = 1; 
+   parameter vco_post_scale = 1;
    parameter vco_frequency_control = "auto";
    parameter vco_phase_shift_step = 0;
    parameter charge_pump_current = 10;
-   parameter loop_filter_r = "1.0";   
-   parameter loop_filter_c = 0;    
+   parameter loop_filter_r = "1.0";
+   parameter loop_filter_c = 0;
    parameter pll_compensation_delay = 0;
    parameter lpm_type = "cycloneiv_pll";
    parameter phase_counter_select_width = 3;
-   
+
    input [1:0] inclk;
    input       fbin;
    input       clkswitch;
@@ -280,7 +280,7 @@ module cycloneiv_pll
    input                                    scanclkena;
    input                                    scandata;
    input                                    configupdate;
-   
+
    output [4:0]                             clk;
    output [1:0]                             clkbad;
    output                                   activeclock;
@@ -293,7 +293,7 @@ module cycloneiv_pll
    output                                   vcounderrange;
    output                                   fref;
    output                                   icdrclk;
-   
+
 endmodule // cycloneive_pll