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| author | dh73 <dh73_fpga@qq.com> | 2017-10-01 11:04:17 -0500 |
|---|---|---|
| committer | dh73 <dh73_fpga@qq.com> | 2017-10-01 11:04:17 -0500 |
| commit | cbaba62401ca975bc9aee91b53e0b48fa59bd6c3 (patch) | |
| tree | cef8519094b97b32e1412647abbd3a09ab0574a2 /techlibs/intel/common/brams.txt | |
| parent | c5b204d8d283d16e6eae8658034da6d378b6810e (diff) | |
| download | yosys-cbaba62401ca975bc9aee91b53e0b48fa59bd6c3.tar.gz yosys-cbaba62401ca975bc9aee91b53e0b48fa59bd6c3.tar.bz2 yosys-cbaba62401ca975bc9aee91b53e0b48fa59bd6c3.zip | |
Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now
Diffstat (limited to 'techlibs/intel/common/brams.txt')
| -rwxr-xr-x | techlibs/intel/common/brams.txt | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/techlibs/intel/common/brams.txt b/techlibs/intel/common/brams.txt new file mode 100755 index 000000000..3bf21afc9 --- /dev/null +++ b/techlibs/intel/common/brams.txt @@ -0,0 +1,33 @@ +bram $__M9K_ALTSYNCRAM_SINGLEPORT_FULL + init 1 + abits 13 @M1 + dbits 1 @M1 + abits 12 @M2 + dbits 2 @M2 + abits 11 @M3 + dbits 4 @M3 + abits 10 @M4 + dbits 8 @M4 + abits 10 @M5 + dbits 9 @M5 + abits 9 @M6 + dbits 16 @M6 + abits 9 @M7 + dbits 18 @M7 + abits 8 @M8 + dbits 32 @M8 + abits 8 @M9 + dbits 36 @M9 + groups 2 + ports 1 1 + wrmode 0 1 + enable 1 1 + transp 0 0 + clocks 2 3 + clkpol 2 3 +endbram + +match $__M9K_ALTSYNCRAM_SINGLEPORT_FULL + min efficiency 2 + make_transp +endmatch |