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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-27 16:07:14 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-27 16:07:14 -0700 |
| commit | 9398921af1d21b47aa291d240a1f274418adcaf2 (patch) | |
| tree | c93649f494e78cb7745a0f64ce8a04443969cff2 /techlibs/ice40 | |
| parent | 550760cc721e8a617e5ca60b3dda70a223504765 (diff) | |
| download | yosys-9398921af1d21b47aa291d240a1f274418adcaf2.tar.gz yosys-9398921af1d21b47aa291d240a1f274418adcaf2.tar.bz2 yosys-9398921af1d21b47aa291d240a1f274418adcaf2.zip | |
Refactor for one "abc_carry" attribute on module
Diffstat (limited to 'techlibs/ice40')
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 317ae2c1f..c7e4101e1 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -136,8 +136,8 @@ module SB_LUT4 (output O, input I0, I1, I2, I3); assign O = I0 ? s1[1] : s1[0]; endmodule -(* abc_box_id = 1, abc_carry, lib_whitebox *) -module SB_CARRY ((* abc_carry_out *) output CO, input I0, I1, (* abc_carry_in *) input CI); +(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *) +module SB_CARRY (output CO, input I0, I1, CI); assign CO = (I0 && I1) || ((I0 || I1) && CI); endmodule |