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| author | Clifford Wolf <clifford@clifford.at> | 2019-02-19 13:42:21 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-02-19 14:47:27 +0100 |
| commit | 62493c91b24c1775f82e64712bf42b175944fe08 (patch) | |
| tree | 8f172dd5466679ef1bc8d88279ca4de052a34c6e /techlibs/ice40/tests/test_dsp_model.sh | |
| parent | 5a853ed46cd3a41df9da4c8206f9416748788487 (diff) | |
| download | yosys-62493c91b24c1775f82e64712bf42b175944fe08.tar.gz yosys-62493c91b24c1775f82e64712bf42b175944fe08.tar.bz2 yosys-62493c91b24c1775f82e64712bf42b175944fe08.zip | |
Add first draft of functional SB_MAC16 model
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'techlibs/ice40/tests/test_dsp_model.sh')
| -rw-r--r-- | techlibs/ice40/tests/test_dsp_model.sh | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/techlibs/ice40/tests/test_dsp_model.sh b/techlibs/ice40/tests/test_dsp_model.sh new file mode 100644 index 000000000..ad079b2b6 --- /dev/null +++ b/techlibs/ice40/tests/test_dsp_model.sh @@ -0,0 +1,6 @@ +#!/bin/bash +set -ex +sed 's/SB_MAC16/SB_MAC16_UUT/; /SB_MAC16_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v +cat /opt/lscc/iCEcube2.2017.01/verilog/sb_ice_syn.v > test_dsp_model_ref.v +iverilog -s testbench -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v +./test_dsp_model |