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| author | N. Engelhardt <nak@yosyshq.com> | 2022-08-25 11:41:12 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-08-25 11:41:12 +0200 |
| commit | 8e640663d6b7ff84043068f48ed5f3cf7bff4321 (patch) | |
| tree | 59001b194c2f573674c37352733427a3ec28a1c1 /techlibs/ice40/synth_ice40.cc | |
| parent | 029c2785e810fda0ccc5abbb6057af760f2fc6f3 (diff) | |
| parent | 9465b2af95a146f514fc1e0b2d31bc3d9a233fb7 (diff) | |
| download | yosys-8e640663d6b7ff84043068f48ed5f3cf7bff4321.tar.gz yosys-8e640663d6b7ff84043068f48ed5f3cf7bff4321.tar.bz2 yosys-8e640663d6b7ff84043068f48ed5f3cf7bff4321.zip | |
Merge pull request #3457 from KrystalDelusion/docs_width
Diffstat (limited to 'techlibs/ice40/synth_ice40.cc')
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 1174f6e04..2ae859efe 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -45,8 +45,8 @@ struct SynthIce40Pass : public ScriptPass log("This command runs synthesis for iCE40 FPGAs.\n"); log("\n"); log(" -device < hx | lp | u >\n"); - log(" relevant only for '-abc9' flow, optimise timing for the specified device.\n"); - log(" default: hx\n"); + log(" relevant only for '-abc9' flow, optimise timing for the specified\n"); + log(" device. default: hx\n"); log("\n"); log(" -top <module>\n"); log(" use the specified module as top module\n"); |