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| author | Clifford Wolf <clifford@clifford.at> | 2016-05-06 23:02:37 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-05-06 23:02:37 +0200 |
| commit | 6fe3d5a1cf938081110db0470def2b2687dd665f (patch) | |
| tree | 16803fc7b1fd542af0e338c127e199515d0c7eb8 /techlibs/ice40/latches_map.v | |
| parent | d10dfccabb6bf4b1ba3f334b899f57093b8a0ddc (diff) | |
| download | yosys-6fe3d5a1cf938081110db0470def2b2687dd665f.tar.gz yosys-6fe3d5a1cf938081110db0470def2b2687dd665f.tar.bz2 yosys-6fe3d5a1cf938081110db0470def2b2687dd665f.zip | |
Added synth_ice40 support for latches via logic loops
Diffstat (limited to 'techlibs/ice40/latches_map.v')
| -rw-r--r-- | techlibs/ice40/latches_map.v | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/techlibs/ice40/latches_map.v b/techlibs/ice40/latches_map.v new file mode 100644 index 000000000..c28f88cf7 --- /dev/null +++ b/techlibs/ice40/latches_map.v @@ -0,0 +1,11 @@ +module \$_DLATCH_N_ (E, D, Q); + wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; + input E, D; + output Q = !E ? D : Q; +endmodule + +module \$_DLATCH_P_ (E, D, Q); + wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; + input E, D; + output Q = E ? D : Q; +endmodule |