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| author | Clifford Wolf <clifford@clifford.at> | 2016-07-08 14:41:36 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-07-08 14:41:36 +0200 |
| commit | 21659847a7a31f80140e03a5b6351da54c062836 (patch) | |
| tree | a40429eac94656936bd48dc26d964b86b1aab8e6 /techlibs/ice40/ice40_ffssr.cc | |
| parent | 9a101dc1f78acb404cc98e0acc4530c238070fd8 (diff) | |
| download | yosys-21659847a7a31f80140e03a5b6351da54c062836.tar.gz yosys-21659847a7a31f80140e03a5b6351da54c062836.tar.bz2 yosys-21659847a7a31f80140e03a5b6351da54c062836.zip | |
Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiations
Diffstat (limited to 'techlibs/ice40/ice40_ffssr.cc')
| -rw-r--r-- | techlibs/ice40/ice40_ffssr.cc | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/techlibs/ice40/ice40_ffssr.cc b/techlibs/ice40/ice40_ffssr.cc index 9a6d69df0..9afbc0fce 100644 --- a/techlibs/ice40/ice40_ffssr.cc +++ b/techlibs/ice40/ice40_ffssr.cc @@ -81,7 +81,12 @@ struct Ice40FfssrPass : public Pass { for (auto cell : ff_cells) { - SigBit bit_d = sigmap(cell->getPort("\\D")); + SigSpec sig_d = cell->getPort("\\D"); + + if (GetSize(sig_d) < 1) + continue; + + SigBit bit_d = sigmap(sig_d[0]); if (sr_muxes.count(bit_d) == 0) continue; |