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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 11:23:31 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 11:23:31 -0700 |
| commit | 0d0ad158984ddc3f66f895b6c18a62f250d2248e (patch) | |
| tree | 7e45b771aecfd21f18fbad10205837d64dcd3f38 /techlibs/ice40/cells_sim.v | |
| parent | a0d85393e388e3349ea501878605e47513ad1699 (diff) | |
| parent | a270af00cc133ac03ec97cf81ed0a7146b7b225e (diff) | |
| download | yosys-0d0ad158984ddc3f66f895b6c18a62f250d2248e.tar.gz yosys-0d0ad158984ddc3f66f895b6c18a62f250d2248e.tar.bz2 yosys-0d0ad158984ddc3f66f895b6c18a62f250d2248e.zip | |
Merge branch 'master' into mwk/xilinx_bufgmap
Diffstat (limited to 'techlibs/ice40/cells_sim.v')
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index ab04808f4..c7f3bdad2 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -143,11 +143,13 @@ endmodule (* abc_box_id = 1, lib_whitebox *) module \$__ICE40_FULL_ADDER ( - (* abc_carry *) output CO, + (* abc_carry *) + output CO, output O, input A, input B, - (* abc_carry *) input CI + (* abc_carry *) + input CI ); SB_CARRY carry ( .I0(A), |