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| author | Tim 'mithro' Ansell <me@mith.ro> | 2018-04-18 16:48:05 -0700 |
|---|---|---|
| committer | Tim 'mithro' Ansell <me@mith.ro> | 2018-04-18 16:55:12 -0700 |
| commit | d6bdefd2e93ad25fd63103d4b76a5573debc6d03 (patch) | |
| tree | 544397a34a4262465eb12b350469a9f63c0b19aa /techlibs/ice40/cells_map.v | |
| parent | ca39e493ba78e7a4eaf3f0876321f892cce20f65 (diff) | |
| download | yosys-d6bdefd2e93ad25fd63103d4b76a5573debc6d03.tar.gz yosys-d6bdefd2e93ad25fd63103d4b76a5573debc6d03.tar.bz2 yosys-d6bdefd2e93ad25fd63103d4b76a5573debc6d03.zip | |
Improving vpr output support.
* Support output BLIF for Xilinx architectures.
* Support using .names in BLIF for Xilinx architectures.
* Use the same `NO_LUT` define in both `synth_ice40` and
`synth_xilinx`.
Diffstat (limited to 'techlibs/ice40/cells_map.v')
| -rw-r--r-- | techlibs/ice40/cells_map.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v index 6550b75cf..d0ddfd02e 100644 --- a/techlibs/ice40/cells_map.v +++ b/techlibs/ice40/cells_map.v @@ -27,7 +27,7 @@ module \$__DFFE_NP1 (input D, C, E, R, output Q); SB_DFFNES _TECHMAP_REPLACE_ ( module \$__DFFE_PP0 (input D, C, E, R, output Q); SB_DFFER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); endmodule module \$__DFFE_PP1 (input D, C, E, R, output Q); SB_DFFES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(R)); endmodule -`ifndef NO_SB_LUT4 +`ifndef NO_LUT module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; |