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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-17 11:10:20 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-17 11:10:20 -0700 |
| commit | c1ebe51a75ef8ce47d6b1406fa87b15bd8f97760 (patch) | |
| tree | 1be2238ddc2e0ae0991df823e807a5baa820ab49 /techlibs/ice40/cells_map.v | |
| parent | a7632ab3326c5247b8152a53808413b259c13253 (diff) | |
| download | yosys-c1ebe51a75ef8ce47d6b1406fa87b15bd8f97760.tar.gz yosys-c1ebe51a75ef8ce47d6b1406fa87b15bd8f97760.tar.bz2 yosys-c1ebe51a75ef8ce47d6b1406fa87b15bd8f97760.zip | |
Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues"
This reverts commit a7632ab3326c5247b8152a53808413b259c13253.
Diffstat (limited to 'techlibs/ice40/cells_map.v')
| -rw-r--r-- | techlibs/ice40/cells_map.v | 24 |
1 files changed, 0 insertions, 24 deletions
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v index d4c611686..d0ddfd02e 100644 --- a/techlibs/ice40/cells_map.v +++ b/techlibs/ice40/cells_map.v @@ -57,27 +57,3 @@ module \$lut (A, Y); endgenerate endmodule `endif - -`ifndef NO_CARRY -module ICE40_CARRY_LUT (output CO, O, input CI, I1, I2); - SB_CARRY carry ( - .I0(I1), - .I1(I2), - .CI(CI), - .CO(CO), - ); - SB_LUT4 #( - // I0: 1010 1010 1010 1010 - // I1: 1100 1100 1100 1100 - // I2: 1111 0000 1111 0000 - // I3: 1111 1111 0000 0000 - .LUT_INIT(16'b 0110_1001_1001_0110) - ) adder ( - .I0(1'b0), - .I1(I1), - .I2(I2), - .I3(CI), - .O(O) - ); -endmodule -`endif |