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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 14:50:59 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 16:29:38 -0700 |
| commit | 6b314c8371bbd8bb999f5ad330aa71c803755d54 (patch) | |
| tree | 25553d72254e4ecbb542282542579d083602d9c8 /techlibs/ice40/cells_map.v | |
| parent | 3414ee1e3fe37d4bf383621542828d4fc8fc987f (diff) | |
| download | yosys-6b314c8371bbd8bb999f5ad330aa71c803755d54.tar.gz yosys-6b314c8371bbd8bb999f5ad330aa71c803755d54.tar.bz2 yosys-6b314c8371bbd8bb999f5ad330aa71c803755d54.zip | |
Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER
Diffstat (limited to 'techlibs/ice40/cells_map.v')
| -rw-r--r-- | techlibs/ice40/cells_map.v | 22 |
1 files changed, 10 insertions, 12 deletions
diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v index b4b831165..511b7f6c6 100644 --- a/techlibs/ice40/cells_map.v +++ b/techlibs/ice40/cells_map.v @@ -62,7 +62,7 @@ module \$lut (A, Y); endmodule `endif -`ifdef _ABC +`ifndef NO_ADDER module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI); SB_CARRY carry ( .I0(A), @@ -70,18 +70,16 @@ module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI); .CI(CI), .CO(CO) ); - SB_LUT4 #( - // I0: 1010 1010 1010 1010 - // I1: 1100 1100 1100 1100 - // I2: 1111 0000 1111 0000 - // I3: 1111 1111 0000 0000 - .LUT_INIT(16'b 0110_1001_1001_0110) + \$lut #( + .WIDTH(4), + // A[0]: 1010 1010 1010 1010 + // A[1]: 1100 1100 1100 1100 + // A[2]: 1111 0000 1111 0000 + // A[3]: 1111 1111 0000 0000 + .LUT(16'b 0110_1001_1001_0110) ) adder ( - .I0(1'b0), - .I1(A), - .I2(B), - .I3(CI), - .O(O) + .A({CI,B,A,1'b0}), + .Y(O) ); endmodule `endif |