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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-08 07:58:11 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-08 07:58:11 -0700 |
| commit | 61d7f1997ba7e3098acc25694accdd0ff25b8ab1 (patch) | |
| tree | 9f61784ace2ff54c0f6cd3705804f13af41f964c /techlibs/ice40/arith_map.v | |
| parent | 3414ee1e3fe37d4bf383621542828d4fc8fc987f (diff) | |
| parent | 8bf45f34c4d7143c58acde2544603cde443ad142 (diff) | |
| download | yosys-61d7f1997ba7e3098acc25694accdd0ff25b8ab1.tar.gz yosys-61d7f1997ba7e3098acc25694accdd0ff25b8ab1.tar.bz2 yosys-61d7f1997ba7e3098acc25694accdd0ff25b8ab1.zip | |
Merge pull request #1266 from YosysHQ/eddie/ice40_full_adder
Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER
Diffstat (limited to 'techlibs/ice40/arith_map.v')
| -rw-r--r-- | techlibs/ice40/arith_map.v | 30 |
1 files changed, 8 insertions, 22 deletions
diff --git a/techlibs/ice40/arith_map.v b/techlibs/ice40/arith_map.v index fe83a8e38..26b24db9e 100644 --- a/techlibs/ice40/arith_map.v +++ b/techlibs/ice40/arith_map.v @@ -44,35 +44,21 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO); genvar i; generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice -`ifdef _ABC - \$__ICE40_FULL_ADDER carry ( + \$__ICE40_CARRY_WRAPPER #( + // A[0]: 1010 1010 1010 1010 + // A[1]: 1100 1100 1100 1100 + // A[2]: 1111 0000 1111 0000 + // A[3]: 1111 1111 0000 0000 + .LUT(16'b 0110_1001_1001_0110) + ) fadd ( .A(AA[i]), .B(BB[i]), .CI(C[i]), - .CO(CO[i]), - .O(Y[i]) - ); -`else - SB_CARRY carry ( - .I0(AA[i]), - .I1(BB[i]), - .CI(C[i]), - .CO(CO[i]) - ); - SB_LUT4 #( - // I0: 1010 1010 1010 1010 - // I1: 1100 1100 1100 1100 - // I2: 1111 0000 1111 0000 - // I3: 1111 1111 0000 0000 - .LUT_INIT(16'b 0110_1001_1001_0110) - ) adder ( .I0(1'b0), - .I1(AA[i]), - .I2(BB[i]), .I3(C[i]), + .CO(CO[i]), .O(Y[i]) ); -`endif end endgenerate assign X = AA ^ BB; |