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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-29 11:26:22 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-09-29 11:26:22 -0700 |
| commit | 8474c5b366660153cae03a9de4af8e1ed809856d (patch) | |
| tree | cd157ab16b528565ced19f422ffece1c6110f53e /techlibs/ice40/Makefile.inc | |
| parent | ce0631c371f69f0132ea9ee4bc8f5ee576dbb1a3 (diff) | |
| parent | b3d8a60cbd94176076f23c4ea6c94ec24e6773e0 (diff) | |
| download | yosys-8474c5b366660153cae03a9de4af8e1ed809856d.tar.gz yosys-8474c5b366660153cae03a9de4af8e1ed809856d.tar.bz2 yosys-8474c5b366660153cae03a9de4af8e1ed809856d.zip | |
Merge pull request #1359 from YosysHQ/xc7dsp
DSP inference for Xilinx (improved for ice40, initial support for ecp5)
Diffstat (limited to 'techlibs/ice40/Makefile.inc')
| -rw-r--r-- | techlibs/ice40/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc index 76a89b107..92a9956ea 100644 --- a/techlibs/ice40/Makefile.inc +++ b/techlibs/ice40/Makefile.inc @@ -27,6 +27,7 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v)) +$(eval $(call add_share_file,share/ice40,techlibs/ice40/dsp_map.v)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.box)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.lut)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_lp.box)) |